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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
DSP core
biblio
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency
biblio
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores
Submitted by aekwall on Mon, 12/02/2019 - 12:07pm
simulated annealing
fault security
Finite impulse response filters
high performance devices
integrated circuit layout
integrated circuit reliability
low-power electronics
optimized low cost transient fault tolerant DSP core
optimized transient fault tolerant DSP
electronic device realibility
simulated annealing based floorplan
simulated annealing based optimization process
sub-nanometer technology scale
technology scaling
Transient fault
transient fault tolerant approach
compiler security
program compilers
Resiliency
pubcrawl
Metrics
Transient analysis
delays
fault tolerance
Fault tolerant systems
Compositionality
Scalability
battery operated low power
battery operated low power high performance devices
circuit optimisation
compiler driven transformation
contradictory design goal optimization
digital signal processing chips
DSP core
