| Title | Reusable intellectual property core protection for both buyer and seller |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Sengupta, Anirban, Roy, Dipanjan |
| Conference Name | 2018 IEEE International Conference on Consumer Electronics (ICCE) |
| Keywords | architectural synthesis process, buyer fingerprint, CE devices, composability, Consumer electronics, design cost overhead, Embedded systems, Fingerprint recognition, Human Behavior, human factors, intellectual property, IP core design, IP core protection, IP networks, ip protection, IP seller, latency overhead, logic circuits, logic design, Metrics, microprocessor chips, policy-based governance, pubcrawl, register allocation phase, Registers, resilience, Resiliency, Resource management, reusable intellectual property core protection, scheduling phase, seller watermark, Watermarking |
| Abstract | This paper presents a methodology for IP core protection of CE devices from both buyer's and seller's perspective. In the presented methodology, buyer fingerprint is embedded along seller watermark during architectural synthesis phase of IP core design. The buyer fingerprint is inserted during scheduling phase while seller watermark is implanted during register allocation phase of architectural synthesis process. The presented approach provides a robust mechanisms of IP core protection for both buyer and seller at zero area overhead, 1.1 % latency overhead and 0.95 % design cost overhead compared to a similar approach (that provides only protection to IP seller). |
| DOI | 10.1109/ICCE.2018.8326059 |
| Citation Key | sengupta_reusable_2018 |
Reusable intellectual property core protection for both buyer and seller