Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy
Title | Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy |
Publication Type | Conference Paper |
Year of Publication | 2018 |
Authors | Shey, James, Karimi, Naghmeh, Robucci, Ryan, Patel, Chintan |
Conference Name | 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Date Published | jul |
Keywords | Benchmark testing, circuit CAD, composability, Computer crime, cryptography, design-based fingerprinting, Fingerprinting, fingerprinting scheme, gate-level netlist changes, Hardware, Human Behavior, human factors, IC design flow, IC piracy, industrial property, integrated circuit design, Integrated circuit modeling, integrated circuit modelling, integrated circuit testing, integrated circuits, Inverters, IP piracy, ip protection, IP/IC providers, learning (artificial intelligence), Logic gates, machine learning, machine learning methods, Metrics, minimal design variations, modified netlist, policy-based governance, pubcrawl, resilience, Resiliency, side-channel power analysis, Supply chains, Trojan horses |
Abstract | Intellectual property (IP) and integrated circuit (IC) piracy are of increasing concern to IP/IC providers because of the globalization of IC design flow and supply chains. Such globalization is driven by the cost associated with the design, fabrication, and testing of integrated circuits and allows avenues for piracy. To protect the designs against IC piracy, we propose a fingerprinting scheme based on side-channel power analysis and machine learning methods. The proposed method distinguishes the ICs which realize a modified netlist, yet same functionality. Our method doesn't imply any hardware overhead. We specifically focus on the ability to detect minimal design variations, as quantified by the number of logic gates changed. Accuracy of the proposed scheme is greater than 96 percent, and typically 99 percent in detecting one or more gate-level netlist changes. Additionally, the effect of temperature has been investigated as part of this work. Results depict 95.4 percent accuracy in detecting the exact number of gate changes when data and classifier use the same temperature, while training with different temperatures results in 33.6 percent accuracy. This shows the effectiveness of building temperature-dependent classifiers from simulations at known operating temperatures. |
DOI | 10.1109/ISVLSI.2018.00117 |
Citation Key | shey_design-based_2018 |
- machine learning methods
- integrated circuit modelling
- integrated circuit testing
- integrated circuits
- Inverters
- ip protection
- IP/IC providers
- learning (artificial intelligence)
- Logic gates
- machine learning
- Integrated circuit modeling
- Metrics
- minimal design variations
- modified netlist
- pubcrawl
- resilience
- side-channel power analysis
- supply chains
- Trojan horses
- fingerprinting scheme
- policy-based governance
- composability
- IP piracy
- Benchmark testing
- circuit CAD
- Computer crime
- Cryptography
- design-based fingerprinting
- Fingerprinting
- Resiliency
- gate-level netlist changes
- Hardware
- Human behavior
- Human Factors
- IC design flow
- IC piracy
- industrial property
- integrated circuit design