High Performance Data Encryption with AES Implementation on FPGA

Submitted by grigby1 on Tue, 12/01/2020 - 12:46pm

Title	High Performance Data Encryption with AES Implementation on FPGA
Publication Type	Conference Paper
Year of Publication	2019
Authors	Chen, S., Hu, W., Li, Z.
Conference Name	2019 IEEE 5th Intl Conference on Big Data Security on Cloud (BigDataSecurity), IEEE Intl Conference on High Performance and Smart Computing, (HPSC) and IEEE Intl Conference on Intelligent Data and Security (IDS)
Date Published	May 2019
Publisher	IEEE
ISBN Number	978-1-7281-0006-7
Keywords	AES, AES encryption algorithm, AES implementation, Big Data, BIGDATA, composability, cryptography, Data security, Encryption, encryption speed, field programmable gate arrays, FPGA, high performance data encryption, high speed, IDS, intrusion detection system, low latency, Pipelines, pubcrawl, Random access memory, resilience, Resiliency
Abstract	Nowadays big data has getting more and more attention in both the academic and the industrial research. With the development of big data, people pay more attention to data security. A significant feature of big data is the large size of the data. In order to improve the encryption speed of the large size of data, this paper uses the deep pipeline and full expansion technology to implement the AES encryption algorithm on FPGA. Achieved throughput of 31.30 Gbps with a minimum latency of 0.134 us. This design can quickly encrypt large amounts of data and provide technical support for the development of big data.
URL	https://ieeexplore.ieee.org/document/8819451
DOI	10.1109/BigDataSecurity-HPSC-IDS.2019.00036
Citation Key	chen_high_2019

Groups:

Science of Security VO