| Title | A Hardware Implementation of the SHA2 Hash Algorithms Using CMOS 28nm Technology |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Brazhnikov, S. |
| Conference Name | 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) |
| Keywords | adders, CMOS 28nm technology, CMOS integrated circuits, CMOS technology, compositionality, cryptography, field programmable gate arrays, Hardware, hardware hash accelerator, Hardware Implementation, hash algorithms, Hash functions, Program processors, pubcrawl, Resiliency, secure hash algorithm 2, SHA-256, SHA2 Hash algorithms |
| Abstract | This article presents a hardware implementation review of a popular family of hash algorithms: Secure Hash Algorithm 2 (SHA2). It presents various schematic solutions and their assessments for 28 nm CMOS technology. Using this paper we can estimate the expected performance of the hardware hash accelerator based on the IC. |
| DOI | 10.1109/EIConRus49466.2020.9039083 |
| Citation Key | brazhnikov_hardware_2020 |
A Hardware Implementation of the SHA2 Hash Algorithms Using CMOS 28nm Technology