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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Hardware Implementation
biblio
Efficient Serial Architecture for PRESENT Block Cipher
Submitted by aekwall on Fri, 03/03/2023 - 11:02am
lightweight cryptography
VHDL
Throughput
side-channel attacks
Scalability
Resiliency
pubcrawl
PRESENT algorithm
Power demand
Ciphers
Lightweight Ciphers
Internet of Things (IoT)
Hardware Implementation
Hardware
FPGA
encryption
cyber-physical systems
biblio
A Secure Network Interface for on-Chip Systems
Submitted by aekwall on Thu, 09/30/2021 - 11:42am
lED
network on chip security
VHDL
Network interfaces
network interface
Multicore processing
Hardware Implementation
decryption
network-on-chip
light emitting diodes
security
Ciphers
AES
Resiliency
Metrics
Scalability
pubcrawl
encryption
tools
computer architecture
biblio
A Hardware Implementation of the SHA2 Hash Algorithms Using CMOS 28nm Technology
Submitted by aekwall on Mon, 03/29/2021 - 12:06pm
Hardware Implementation
SHA2 Hash algorithms
SHA-256
secure hash algorithm 2
hardware hash accelerator
CMOS 28nm technology
hash algorithms
Hash functions
adders
field programmable gate arrays
Compositionality
pubcrawl
CMOS technology
CMOS integrated circuits
Resiliency
Program processors
Hardware
Cryptography
biblio
Hardware Implementation of Cancellable Biometric Systems
Submitted by aekwall on Tue, 03/09/2021 - 11:56am
FPGA model
Watermarking
Three-dimensional displays
security systems
security applications
Scalability
Resiliency
pubcrawl
one-way cancellable biometric template system
Metrics
Information encryption
Hardware Implementation
Hardware
biometric encryption
FPGA
fingerprint encryption
field programmable gate arrays
face encryption
encryption
Cryptography
Cancellable biometrics
biometrics (access control)
Biological system modeling
3D chaotic mapping
3D chaotic map
biblio
Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA
Submitted by grigby1 on Fri, 09/04/2020 - 3:37pm
32/34/26-instance parallelization
brute force attacks
single Virtex-7 FPGA device
pre-image brute-force attack
pipeline processing
MD5 hash generation
MD5 hash algorithm
LUT
IP core
HDL
Hardware design languages
guess password generation
Cryptography
field programmable gate arrays
gpu
policy-based governance
Human Factors
password
pubcrawl
Generators
Hardware
computer architecture
Hardware Implementation
biblio
Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application
Submitted by aekwall on Mon, 02/10/2020 - 11:44am
piccolo encryption algorithm
4 input LUTs
64 bits block size
area optimization
ASIC
constrained RFID application
different design strategies
efficient hardware architecture
Fiestel structure
hardware design
hardware metrics
low resource applications
optimized area
Piccolo Algorithm
128 bits
piccolo lightweight algorithm
radiofrequency identification
relevant lightweight block ciphers
severe security concerns
supports high speed
Throughput.
tremendous pace
ultra-lightweight applications
variable key size
word length 64.0 bit
word length 80.0 bit
Xillinx
Microelectronics Security
security applications
field programmable gate arrays
FPGA
Cryptography
encryption
Internet of Things
telecommunication security
Hardware
Table lookup
IoT applications
smart devices
Resiliency
pubcrawl
composability
IoT
RFID
Throughput
Ciphers
security issues
Predictive Metrics
private information
word length 128.0 bit
Hardware Implementation
hardware resources
lightweight cryptographic algorithms
S-box
lightweight cryptography
biblio
Comparative Analysis of Lightweight Block Ciphers in IoT-Enabled Smart Environment
Submitted by aekwall on Mon, 01/20/2020 - 11:58am
privacy
ultra-lightweight block ciphers
Software
smart computing environment
signal processing
security solutions
security in resource-constrained environment
Schedules
Scalability
resource-constrained environment
Resiliency
real-life things
rapid technological growth
pubcrawl
32-bit cipher
lightweight cryptography
lightweight cryptographic solutions
Lightweight Ciphers
lightweight block ciphers
IoT-enabled smart environment
Internet of Things
Hardware Implementation
encryption
Cryptography
Comparative Analysis
Ciphers
32-bit ultra-lightweight block cipher security model
biblio
Hardware Implementation of A Chaotic Pseudo Random Number Generator Based on 3D Chaotic System without Equilibrium
Submitted by aekwall on Mon, 11/25/2019 - 2:09pm
lightweight systems
chaotic pseudorandom number generator
cryptography systems
deterministic chaotic systems
digital communication
digital communication systems
dynamical behavior
Dynamical Systems
Hardware Implementation
chaotic dynamics
low computational overhead
low-cost chaotic hardware
low-cost hardware platforms
simple nonlinear systems
three-dimensional chaotic flows
Three-dimensional displays
chaotic cryptography
field programmable gate arrays
chaotic behaviors
chaotic based digital systems
3D chaotic system
3D chaotic flows
chaotic communication
Predictive Metrics
random number generation
Generators
Mathematical model
composability
pubcrawl
Resiliency
embedded systems
Hardware
Cryptography
biblio
Implementation of Searchable Encryption System with Dedicated Hardware and Its Evaluation
Submitted by grigby1 on Thu, 09/26/2019 - 10:27am
database management systems
shared database
searchable encryption system
Medical services
Hardware Implementation
encrypted data
dedicated hardware
symmetric searchable encryption
public key encryption with keyword search
Big Data
personal information
searchable encryption
Artificial Intelligence
Cryptography
composability
Resiliency
pubcrawl
resilience
biblio
SRAM voltage scaling for energy-efficient convolutional neural networks
Submitted by grigby1 on Thu, 06/07/2018 - 3:06pm
Si
memory power intensive
memory size 8 KByte
Micromechanical devices
neural nets
Neural Network Resilience
pubcrawl
Random access memory
resilience
Resiliency
low-power embedded system
Silicon
silicon-on-insulator
size 28 nm
SRAM chips
SRAM voltage scaling
Training
UTBB FD-SOI CMOS
voltage 310 mV
energy-efficient convolutional neural network
bit error injection
Bit error rate
CMOS memory circuits
ConvNet training
convolutional neural networks
deep learning
electronic engineering computing
elemental semiconductors
energy conservation
approximate SRAM
energy-quality tradeoff
error resiliency
floating-point classification accuracy
Hardware
Hardware Implementation
IoE platform
learning (artificial intelligence)
low-power electronics
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