| Title | Design and synthesis of FIR filter banks using area and power efficient Stochastic Computing |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Mahesh, V V, Shahana, T K |
| Conference Name | 2020 Fourth World Conference on Smart Trends in Systems, Security and Sustainability (WorldS4) |
| Keywords | delays, Filter banks, finite impulse response filter, Finite impulse response filters, Generators, Hardware, linear feedback shift register, Logic gates, Power filters, pubcrawl, resilience, Resiliency, Stochastic computing, Stochastic Computing Security |
| Abstract | Stochastic computing is based on probability concepts which are different from conventional mathematical operations. Advantages of stochastic computing in the fields of neural networks and digital image processing have been reported in literature recently. Arithmetic operations especially multiplications can be performed either by logical AND gates in unipolar format or by EXNOR gates in bipolar format in stochastic computation. Stochastic computing is inherently fault-tolerant and requires fewer logic gates to implement arithmetic operations. Long computing time and low accuracy are the main drawbacks of this system. In this presentation, to reduce hardware requirement and delay, modified stochastic multiplication using AND gate array and multiplexer are used for the design of Finite Impulse Response Filter cores. Performance parameters such as area, power and delay for FIR filter using modified stochastic computing methods are compared with conventional floating point computation. |
| DOI | 10.1109/WorldS450073.2020.9210403 |
| Citation Key | mahesh_design_2020 |
Design and synthesis of FIR filter banks using area and power efficient Stochastic Computing