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Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

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Visible to the public Hardware Steganography for IP Core Protection of Fault Secured DSP Cores

Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
  • DSP based IP cores
  • vendor defined signature
  • transient fault secured IP cores
  • signature size
  • signature free approach
  • multimedia cores
  • IP core protection
  • IP core
  • high level synthesis
  • hardware steganography
  • fault secured DSP cores
  • Fault secure
  • entropy value
  • entropy thresholding
  • encoding rule
  • Resiliency
  • colored interval graph
  • IP piracy
  • Steganography
  • DSP
  • logic design
  • digital signal processing chips
  • Watermarking
  • industrial property
  • digital signatures
  • Entropy
  • graph theory
  • policy-based governance
  • composability
  • pubcrawl

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