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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
IP core
biblio
A Support Vector Machine Algorithm for PIR Special Processor
Submitted by aekwall on Mon, 12/14/2020 - 11:30am
data processing algorithm
timing design
SVM classification
real-time intellectual property core
pyroelectric infrared sensor
pyroelectric detectors
PIR special processor
PIR sensor
mathematical statistics
infrared products
human motion detection technology
function design
fast Fourier transform
distance 15.0 m
Support vector machines
continuous improvement
algorithm flow
IP core
hardware description languages
Kalman filters
Predictive Metrics
data acquisition
industrial property
microcontrollers
composability
pubcrawl
Resiliency
support vector machine
biblio
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
Submitted by aekwall on Mon, 11/09/2020 - 12:40pm
block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency
biblio
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores
Submitted by aekwall on Mon, 11/09/2020 - 12:40pm
DSP based IP cores
vendor defined signature
transient fault secured IP cores
signature size
signature free approach
multimedia cores
IP core protection
IP core
high level synthesis
hardware steganography
fault secured DSP cores
Fault secure
entropy value
entropy thresholding
encoding rule
Resiliency
colored interval graph
IP piracy
Steganography
DSP
logic design
digital signal processing chips
Watermarking
industrial property
digital signatures
Entropy
graph theory
policy-based governance
composability
pubcrawl
biblio
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning
Submitted by grigby1 on Mon, 11/02/2020 - 11:30am
IP cloning
watermarking approach
system-on-chips
system-on-chip
synthesis
robust digital signature
Resiliency
resilience
pubcrawl
Protection.
policy-based governance
multiple security modules
multimedia based reusable Intellectual property cores
IP core
composability
intellectual property security
industrial property
fraudulent ownership
encryption
encoding
DSP
digital signatures
digital signature processing cores
digital signature
digital signal processing chips
Cryptography
crypto digital signature approach
consumer electronic devices
biblio
Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA
Submitted by grigby1 on Fri, 09/04/2020 - 2:37pm
32/34/26-instance parallelization
brute force attacks
single Virtex-7 FPGA device
pre-image brute-force attack
pipeline processing
MD5 hash generation
MD5 hash algorithm
LUT
IP core
HDL
Hardware design languages
guess password generation
Cryptography
field programmable gate arrays
gpu
policy-based governance
Human Factors
password
pubcrawl
Generators
Hardware
computer architecture
Hardware Implementation
biblio
Privacy-preserving functional IP verification utilizing fully homomorphic encryption
Submitted by grigby1 on Wed, 03/08/2017 - 1:33pm
IP theft
system-on-chip
SoC design
sequential benchmark circuits
security parameter sizes
pubcrawl170112
privacy-preserving version
privacy-preserving functional IP verification
Noise
magnitude IP verification
Logic gates
Libraries
IP users
Cryptography
IP reuse
IP networks
IP core
intellectual property verification
industrial property
IC industry
IC design business model
globalized supply chain
functional verification
fully homomorphic encryption
encryption
data privacy
