Design of Boolean Chaotic Oscillator Using CMOS Technology for True Random Number Generation
| Title | Design of Boolean Chaotic Oscillator Using CMOS Technology for True Random Number Generation |
| Publication Type | Conference Paper |
| Year of Publication | 2017 |
| Authors | Rajagopalan, S., Rethinam, S., Deepika, A. N., Priyadarshini, A., Jyothirmai, M., Rengarajan, A. |
| Conference Name | 2017 International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS) |
| Date Published | aug |
| Publisher | IEEE |
| ISBN Number | 978-1-5386-1716-8 |
| Keywords | 45nm CMOS technology, application specific integrated circuits, authentication security, cadence virtuoso, Cadence Virtuoso tool, Capacitors, chaos, CMOS, CMOS Boolean Chaotic Oscillator Design, CMOS integrated circuits, cryptography, data transmission security, delays, Generators, Human Behavior, Inverters, Logic gates, message authentication, Metrics, National Institute of Standards and Technology, NI ELVIS platform, Oscillators, pubcrawl, random cryptographic keys, random key generation, random number generation, random number generators, random numbers, resilience, Resiliency, Ring oscillators, Scalability, security keys |
| Abstract | True random numbers have a fair role in modern digital transactions. In order to achieve secured authentication, true random numbers are generated as security keys which are highly unpredictable and non-repetitive. True random number generators are used mainly in the field of cryptography to generate random cryptographic keys for secure data transmission. The proposed work aims at the generation of true random numbers based on CMOS Boolean Chaotic Oscillator. As a part of this work, ASIC approach of CMOS Boolean Chaotic Oscillator is modelled and simulated using Cadence Virtuoso tool based on 45nm CMOS technology. Besides, prototype model has been implemented with circuit components and analysed using NI ELVIS platform. The strength of the generated random numbers was ensured by NIST (National Institute of Standards and Technology) Test Suite and ASIC approach was validated through various parameters by performing various analyses such as frequency, delay and power. |
| URL | https://ieeexplore.ieee.org/document/8211590 |
| DOI | 10.1109/ICMDCS.2017.8211590 |
| Citation Key | rajagopalan_design_2017 |
- random number generation
- message authentication
- Metrics
- National Institute of Standards and Technology
- NI ELVIS platform
- Oscillators
- pubcrawl
- random cryptographic keys
- random key generation
- Logic gates
- random number generators
- random numbers
- resilience
- Resiliency
- Ring oscillators
- Scalability
- security keys
- 45nm CMOS technology
- Inverters
- Human behavior
- Generators
- delays
- data transmission security
- Cryptography
- CMOS integrated circuits
- CMOS Boolean Chaotic Oscillator Design
- CMOS
- chaos
- Capacitors
- Cadence Virtuoso tool
- cadence virtuoso
- authentication security
- application specific integrated circuits