| Title | Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip |
| Publication Type | Journal Article |
| Year of Publication | 2018 |
| Authors | Biswas, Arnab Kumar |
| Journal | IEEE Transactions on Parallel and Distributed Systems |
| Volume | 29 |
| Pagination | 1044—1057 |
| Date Published | may |
| ISSN | 1558-2183 |
| Keywords | channel attacks, circuit switching, circuit switching NoC, combined hybrid routers, conventional hybrid router, covert timing channel, hybrid network-on-chip, hybrid NoC, Integrated circuit modeling, Metrics, MP-SoC, multiprocessing systems, multiprocessor system-on-chip, network on chip security, network routing, network transmission, network-on-chip, packet switching, packet switching NoC, packet-circuit-switched, pubcrawl, resilience, Resiliency, Scalability, security in NoC, Separate interface Hybrid, side-channel attacks, Switching circuits, system security policy, TDM, Throughput, Timing, timing channel, timing channel protection, timing characteristics, timing side channel |
| Abstract | Continuous development of Network-on-Chip (NoC) enables different types of applications to run efficiently in a Multiprocessor System-on-Chip (MP-SoC). Guaranteed service (GS) can be provided by circuit switching NoC and Best effort service (BES) can be provided by packet switching NoC. A hybrid NoC containing both packet and circuit switching, can provide both types of services to these different applications. But these different applications can be of different security levels and one application can interfere another application's timing characteristics during network transmission. Using this interference, a malicious application can extract secret information from higher security level flows (timing side channel) or two applications can communicate covertly violating the system's security policy (covert timing channel). We propose different mechanisms to protect hybrid routers from timing channel attacks. For design space exploration, we propose three timing channel secure hybrid routers viz. Separate Hybrid (SH), Combined with Separate interface Hybrid (CSH), and Combined Hybrid (CH) routers. Simulation results show that all three routers are secure from timing channel when compared to a conventional hybrid router. Synthesis results show that the area increments compared to a conventional hybrid router are only 7.63, 11.8, and 19.69 percent for SH, CSH, and CH routers respectively. Thus simulation and synthesis results prove the effectiveness of our proposed mechanisms with acceptable area overheads. |
| DOI | 10.1109/TPDS.2017.2783337 |
| Citation Key | biswas_efficient_2018 |
Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip