Visible to the public Architecting a Secure Wireless Network-on-Chip

TitleArchitecting a Secure Wireless Network-on-Chip
Publication TypeConference Paper
Year of Publication2018
AuthorsLebiednik, Brian, Abadal, Sergi, Kwon, Hyoukjun, Krishna, Tushar
Conference Name2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)
Date PublishedOct. 2018
PublisherIEEE
ISBN Number978-1-5386-4893-3
KeywordsBandwidth, Communication system security, electrical wires, energy benefits, entire chip, Fault tolerance, faulty wireless components, integrated circuit design, Integrated circuit interconnections, latency constraints, Metrics, Multiaccess communication, multiprocessing systems, network interface, network on chip security, network-on-chip, network-on-chip connecting cores, on-chip systems, one-hop broadcasts, point-to-point multihop signaling, Protocols, pubcrawl, resilience, Resiliency, Scalability, security, telecommunication security, traditional wired NoC, wireless channels, Wireless communication, Wireless sensor networks, WNoC
Abstract

With increasing integration in SoCs, the Network-on-Chip (NoC) connecting cores and accelerators is of paramount importance to provide low-latency and high-throughput communication. Due to limits to scaling of electrical wires in terms of energy and delay, especially for long multi-mm distances on-chip, alternate technologies such as Wireless Network-on-Chip (WNoC) have shown promise. WNoCs can provide low-latency one-hop broadcasts across the entire chip and can augment point-to-point multi-hop signaling over traditional wired NoCs. Thus, there has been a recent surge in research demonstrating the performance and energy benefits of WNoCs. However, little to no work has studied the additional security and fault tolerance challenges that are unique to WNoCs. In this work, we study potential threats related to denial-of-service, spoofing, and eavesdropping attacks in WNoCs, due to malicious hardware trojans or faulty wireless components. We introduce Prometheus, a dropin solution inside the network interface that provides protection from all three attacks, while adhering to the strict area, power and latency constraints of on-chip systems.

URLhttp://dx.doi.org/10.1109/NOCS.2018.8512168
DOI10.1109/NOCS.2018.8512168
Citation Keylebiednik_architecting_2018