| Title | Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | J.Y.V., Manoj Kumar, Swain, Ayas Kanta, Kumar, Sudeendra, Sahoo, Sauvagya Ranjan, Mahapatra, Kamalakanta |
| Conference Name | 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
| Date Published | jul |
| Keywords | bit shuffling mechanism, Buffer storage, Computer architecture, cryptographic modules, cryptography, Degradation, denial of service attack, Hardware, hardware security issues, hardware trojan, integrated circuit design, Metrics, microprocessor chips, MPSoC, multiprocessing systems, multiprocessor system on chips, network on chip security, network-on-chip, NoC, performance degradation Hardware Trojan attacks, performance evaluation, pubcrawl, resilience, Resiliency, Router Architecture, run time mitigation, Scalability, security, semiconductor design, system-on-chip, Trojan horses |
| Abstract | Globalization of semiconductor design and manufacturing has led to several hardware security issues. The problem of Hardware Trojans (HT) is one such security issue discussed widely in industry and academia. Adversary design engineer can insert the HT to leak confidential data, cause a denial of service attack or any other intention specific to the design. HT in cryptographic modules and processors are widely discussed. HT in Multi-Processor System on Chips (MPSoC) are also catastrophic, as most of the military applications use MPSoCs. Network on Chips (NoC) are standard communication infrastructure in modern day MPSoC. In this paper, we present a novel hardware Trojan which is capable of inducing performance degradation and denial of service attacks in a NoC. The presence of the Hardware Trojan in a NoC can compromise the crucial details of packets communicated through NoC. The proposed Trojan is triggered by a particular complex bit pattern from input messages and tries to mislead the packets away from the destined addresses. A mitigation method based on bit shuffling mechanism inside the router with a key directly extracted from input message is proposed to limit the adverse effects of the Trojan. The performance of a 4x4 NoC is evaluated under uniform traffic with the proposed Trojan and mitigation method. Simulation results show that the proposed mitigation scheme is useful in limiting the malicious effect of hardware Trojan. |
| DOI | 10.1109/ISVLSI.2018.00139 |
| Citation Key | jyv_run_2018 |
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip