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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
system-on-chip
biblio
On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems
Submitted by aekwall on Wed, 05/01/2019 - 12:42pm
security of data
memory security
Metrics
microprocessor chips
on-chip memory blocks
pubcrawl
reconfigurable logic fabric
Resiliency
security
memory protection unit
security services
SoC FPGA
software IP
static detection methods
system-on-chip
third-party IP cores
third-party IPs
3PIP
memory protection design
memory access
low-latency hardware
IP networks
Intel DE1-SoC board
implementation
hierarchical top-down structure
Hardware
golden reference model
FPGA-based embedded systems
field programmable gate arrays
embedded systems
dual-core ARM processor
Cryptography
composability
biblio
LiteHAX: Lightweight Hardware-Assisted Attestation of Program Execution
Submitted by aekwall on Wed, 02/13/2019 - 11:58am
Runtime
programming
pubcrawl
RA
reduced instruction set computing
remote device integrity
Resiliency
RISC-based embedded devices
RISC-V system-on-chip
Program processors
runtime attestation
security
security of data
security service
SoC
software binaries
system-on-chip
Trusted Computing
embedded Internet of Things devices
composability
control-flow attacks
control-flow attestation schemes
data flow computing
data integrity
data-flow events
data-oriented programming
DOP attacks
attestation
embedded systems
hardware-assisted remote attestation scheme
Human behavior
Internet of Things
lightweight hardware-assisted attestation of program execution
LiteHAX
malicious modification
malware
biblio
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
Submitted by grigby1 on Wed, 09/12/2018 - 11:25am
SIMD
Program processors
Programmable SoC
pubcrawl
real-time on-line pattern search
real-time systems
resilience
Resiliency
Scalability
search problems
platform based design methodologies
string matching
system monitoring
system-on-chip
SystemC
TCP
TCP packets
Xilinx Zynq programmable SoC
Zynq
High-Le'vel Synthesis
Algorithm design and analysis
BM string search algorithm
Boyer-Moore
Boyer-Moore algorithm
computer network security
deep packet inspection
FPGA
Hardware
high level synthesis
Accelerator
high-level synthesis
Inspection
MISD parallelism
Network Monitoring
network security
parallel processing
Payloads
Platform Based Design
biblio
High confinement and low loss Si3N4waveguides for miniaturizing optical coherence tomography
Submitted by grigby1 on Thu, 08/23/2018 - 11:59am
optical tuning
system-on-chip
size 42.0 cm
Silicon compounds
Si3N4
Resiliency
resilience
pubcrawl
Propagation losses
privacy
Optimized production technology
Optical waveguides
composability
optical tomography
optical losses
Optical interferometry
optical coherence tomography
low loss silicon nitride waveguide
Integrated optics
Imaging
high confinement thermally tunable silicon nitride waveguide
cyber-physical systems
confinement
biblio
Smart bluetooth low energy security system
Submitted by grigby1 on Thu, 08/23/2018 - 11:35am
smart phones
PSoC 4 BLE
pubcrawl
resilience
Resiliency
security
sensors
Servomotors
smart Bluetooth low energy security system
physical lock
smartphone
surveillance system
system-on-chip
Web page
Web site
wireless connection
wireless technologies
BLE (Bluetooth Low Energy)
low energy consumption security system
IoT (Internet of Things)
image transmission
human factor
Human behavior
energy security
energy consumption
Conferences
composability
Cameras
building management systems
bluetooth security
Bluetooth
BLE technology
biometric
biblio
Minimum energy quantized neural networks
Submitted by grigby1 on Mon, 06/11/2018 - 3:24pm
iso-accuracy depending
automated minimum-energy optimization
BinaryNets
complex arithmetic
fixed point arithmetic
fundamental trade-off
generic hardware platform
higher precision operators
int4 implementations
int8 networks
arbitrary fixed point precision
low precision weights
Minimum Energy
minimum energy QNN
QNN training
Quantized Neural Network
quantized neural networks
wider network architectures
network on chip security
resilience
Resiliency
Scalability
Hardware
neural nets
energy consumption
telecommunication security
Neural networks
Training
deep learning
pubcrawl
Memory management
Metrics
Random access memory
system-on-chip
energy conservation
power aware computing
Mobile communication
approximate computing
biblio
Study of secure boot with a FPGA-based IoT device
Submitted by grigby1 on Mon, 06/11/2018 - 3:23pm
bitstream decoding
network on chip security
Xilinx Zynq-7000 Series System-on-Chip ZC706 prototype board
Trojan Horse attacks
software-based security implementation
Secure Boot
IoT system
infrastructure components
host processor computation power
FPGA-based IoT device
FPGA design
FPGA bitstream
encrypt system boot image
effective security provisioning
critical components
pubcrawl
system-on-chip
Decoding
Metrics
resilience
system security
field programmable gate arrays
Trojan horses
authentication
encryption
Cryptography
Internet of Things
Scalability
Resiliency
biblio
PUFSec: Protecting physical unclonable functions using hardware isolation-based system security techniques
Submitted by grigby1 on Mon, 06/11/2018 - 3:20pm
physical unclonable function protection
Xilinx SoC
system-on-chip
system security techniques
Software
security protection
security policies
security compromises
security challenges
secure architecture extension
Resiliency
resilience
PUFSec framework
PUF workflow
PUF hardware
pubcrawl
Access Control
Networked Control Systems Security
Monitoring
Modeling Attacks
Metrics
internal PUF design
hardware isolation
Hardware
DoS attacks
Denial of Service attacks
Data protection
control systems
computer network security
computer architecture
composability
ARM Processor
biblio
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with \#x003E;0.1 timing error rate tolerance for IoT applications
Submitted by grigby1 on Thu, 06/07/2018 - 3:07pm
Internet of Things
VDD scaling
timing error rate tolerance
timing
Throughput
system-on-chip
sign-magnitude number format
Resiliency
resilience
Razor timing violation detection
pubcrawl
programmable FC-DNN accelerator design
Program processors
Neural Network Resilience
neural nets
IoT applications
1.2GHz 568nJ/prediction sparse deep-neural-network engine
frequency 667 MHz
frequency 1.2 GHz
frequency 1 GHz
FCLK scaling
Error analysis
Engines
Energy Efficiency
datapath logic
data sparsity
circuit-level timing violation tolerance
circuit resilience
algorithmic resilience
algorithmic error tolerance
aggregate timing violation rates
28nm SoC
biblio
Scalable stochastic-computing accelerator for convolutional neural networks
Submitted by grigby1 on Thu, 06/07/2018 - 3:06pm
pubcrawl
Weight parameter retraining
system-on-chip
Stochastic computing
scalable stochastic-computing accelerator
SC-based neural networks
Resiliency
resilience
Recognition accuracy
arrays
Neural Network Resilience
neural nets
convolutional neural networks
convolutional neural network
convolution
ConvNets
computational complexity
Biological neural networks
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