Visible to the public Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm

TitleProgrammable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
Publication TypeConference Paper
Year of Publication2017
AuthorsDomínguez, A., Carballo, P. P., Núñez, A.
Conference Name2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
PublisherIEEE
ISBN Number978-1-5386-3344-1
KeywordsAccelerator, Algorithm design and analysis, BM string search algorithm, Boyer-Moore, Boyer-Moore algorithm, computer network security, deep packet inspection, FPGA, Hardware, high level synthesis, High-Le'vel Synthesis, high-level synthesis, Inspection, MISD parallelism, network monitoring, Network security, parallel processing, Payloads, Platform Based Design, platform based design methodologies, Program processors, Programmable SoC, pubcrawl, real-time on-line pattern search, Real-time Systems, resilience, Resiliency, Scalability, search problems, SIMD, string matching, system monitoring, system-on-chip, SystemC, TCP, TCP packets, Xilinx Zynq programmable SoC, Zynq
Abstract

This paper describes the work done to design a SoC platform for real-time on-line pattern search in TCP packets for Deep Packet Inspection (DPI) applications. The platform is based on a Xilinx Zynq programmable SoC and includes an accelerator that implements a pattern search engine that extends the original Boyer-Moore algorithm with timing and logical rules, that produces a very complex set of rules. Also, the platform implements different modes of operation, including SIMD and MISD parallelism, which can be configured on-line. The platform is scalable depending of the analysis requirement up to 8 Gbps. High-Level synthesis and platform based design methodologies have been used to reduce the time to market of the completed system.

URLhttps://ieeexplore.ieee.org/document/8016159
DOI10.1109/ReCoSoC.2017.8016159
Citation Keydominguez_programmable_2017