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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
system-on-chip
biblio
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
hardware trojan
Trojan horses
system-on-chip
semiconductor design
security
run time mitigation
performance degradation Hardware Trojan attacks
NoC
network-on-chip
multiprocessor system on chips
multiprocessing systems
MPSoC
microprocessor chips
integrated circuit design
performance evaluation
Router Architecture
pubcrawl
hardware security issues
Hardware
denial of service attack
Degradation
Cryptography
cryptographic modules
computer architecture
Buffer storage
bit shuffling mechanism
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Hardware-Assisted Security in Electronic Control Units: Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
secure execution environments
Firewalls (computing)
Hardware
hardware firewalling
hardware-assisted security
network-on-chip
off-chip networking techniques
on-chip network physical isolation
one-time-programmable network
Secure Automotive Communications
firewalls
smart automotive technologies
software-dominated enhancements
system-level countermeasures
system-on-chip
system-wide cryptographic techniques
threat models
Trusted Electronic Control Units
vehicle-to-vehicle communications
automotive controller area network-bus communications
network on chip security
Scalability
Resiliency
resilience
Metrics
advanced driver assistance systems
authentication
automotive communications
pubcrawl
automotive electronics
Automotive engineering
controller area networks
cyber-enabled automotive system
data privacy
driver information systems
electronic control units
enjoyable driving
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
programming flexibility
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
microprocessor chips
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
cache location
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
pubcrawl
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
biblio
Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks
Submitted by aekwall on Mon, 05/11/2020 - 11:09am
persistent jamming attack
internal hardware Trojans
jamming attack
low-power transceivers
ML classifiers
network-on-chip communications
NoC switches
nonscalable multihop data transmission paths
On chip interconnect
On chip security
on-chip data transfer
on-chip wireless medium
denial-of-service attacks
radio transceivers
radiofrequency interconnections
random burst error correction code
Switches
switching networks
WiNoC security
wired NoC architectures
wireless interconnection
Wireless NoC
wireless NoC architectures
network on chip security
system-on-chip
telecommunication security
learning (artificial intelligence)
Resiliency
pubcrawl
wireless sensor networks
Wireless communication
Metrics
machine learning
telecommunication network routing
telecommunication computing
radio networks
Scalability
DoS
Hardware Security
error correction codes
radiofrequency interference
DoS attack
Jamming
denial-of-service attack
machine learning classifier
HT
network-on-chip
data transfer security threats
biblio
Security Network On-Chip for Mitigating Side-Channel Attacks
Submitted by aekwall on Mon, 05/11/2020 - 11:08am
multiple countermeasures
compromised device
contemporary hardware threats
design complexity
electromagnetic analysis attacks
electromagnetic interference
hardware security threats
high-confidence security network on-chip
individual threats
machine learning security IC
malicious physical interference
modern ICs
attack-specific countermeasures
on-chip distribution networks
On-chip power delivery
on-chip voltage variations
operating device-under-attack
robust confidence security network on-chip
security networks
Side-channel attack
side-channel attack mitigation
strict performance requirements
trained ML ICs
network on chip security
timing
Scalability
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
machine learning
physical interaction
system-on-chip
system security
sensors
Attack detection
security of data
Hardware Security
side-channel attacks
integrated circuit design
data analysis
malicious activity
integrated circuits
network-on-chip
active attack
advance invasive attacks
advance noninvasive attacks
advanced technology nodes
biblio
Alternatives to Fault Injections for Early Safety/Security Evaluations
Submitted by aekwall on Mon, 03/09/2020 - 11:17am
Human Factors
Security Risk Estimation
system dependability constraints
RTL fault injection campaigns
radiation testing
market pressure
ISO 26262
intertwined hardware
HW-SW systems
functional safety standards
fault injections
dependability analysis
cyber physical systems
hardware-software codesign
Circuit faults
CPS
Safety
safety-critical software
ISO standards
cost reduction
Reliability
Metrics
pubcrawl
Resiliency
Time measurement
system-on-chip
SoC
embedded systems
Software
Hardware
Scalability
security of data
biblio
Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection
Submitted by grigby1 on Wed, 02/26/2020 - 4:38pm
pubcrawl
logic locking method
malicious circuits
million-gate circuits
outsourcing
PCA-based HT detection methods
power analysis-based Trojan detection
power consumption
power consumption analysis
Power demand
principal component analysis
Process Variations
logic locking
resilience
security
semiconductor companies
small sub-circuit collection
supply chain security
Switches
system-on-chip
trojan horse detection
Trojan horses
untrustworthy fabs
hardware Trojan detection
policy-based governance
composability
IP piracy
circuit block extraction
circuit power
cyber physical systems
design for hardware trust
fabrication foundries
gate level
Hardware
Hardware Security
Resiliency
hardware Trojan threat
HT activity
HT power
HT-infected circuits
industrial property
integrated circuit layout
intellectual properties
invasive software
IPS
Logic gates
biblio
FIXER: Flow Integrity Extensions for Embedded RISC-V
Submitted by aekwall on Mon, 02/24/2020 - 11:01am
integrated Rocket Custom Coprocessor
program compilers
security framework
RISC-V
buffer overflow
Code injection
coprocessors
fine-grained control-flow integrity
FIXER
flow integrity extensions for embedded RISC-V
return oriented programming
low-power embedded devices
open source architecture
RISC-V architecture
RISC-V processor core
RISC-V SoC platform
RISC-V toolchains
Rockets
security extension
shadow stack
Buffer overflows
Scalability
Internet of Things
data integrity
Hardware
security
embedded systems
reduced instruction set computing
system-on-chip
computer architecture
security of data
Resiliency
pubcrawl
composability
software reusability
Software Architecture
Bars
Human Factors
code reuse attacks
ROP
biblio
An Efficient Memory Zeroization Technique Under Side-Channel Attacks
Submitted by aekwall on Mon, 02/24/2020 - 10:55am
built-in self test
volatile memories
side-channel attacks
Side-channel attack
security violations
secured data content
secret data
random-access storage
private memory contents
on-chip memory contents
Memory Zeroization
memory security
memory built-in-self-test hardware
MBIST based content zeroization approach
efficient memory zeroization technique
content protection
security of data
Temperature sensors
cryptographic keys
remanence
Compositionality
Engines
Random access memory
data deletion
security attacks
pubcrawl
Resiliency
system-on-chip
security
Memory management
Hardware
Cryptography
biblio
Multi-core Heterogeneous Video Processing System Design
Submitted by aekwall on Mon, 02/10/2020 - 11:58am
image binarization
multicore computing security
Zynq
Xilinx Zynq platform
real-time video image processing system
Otsu binarized hardware-accelerated IP
otsu adaptive binarization
multicore heterogeneous video processing system design
multicore heterogeneous computing technology
multicore heterogeneous acceleration processing
multi-core heterogeneous
image processing speed
field programmable gate arrays
hardware acceleration
multiprocessing systems
microprocessor chips
video signal processing
Metrics
pubcrawl
Resiliency
system-on-chip
Scalability
IP networks
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