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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
system-on-chip
biblio
Run-time Detection and Mitigation of Power-Noise Viruses
Submitted by aekwall on Mon, 02/10/2020 - 10:58am
data corruptions
multicore computing security
voltage noise data
voltage emergencies
Viruses (medical)
Threshold voltage
system crashes
run-time system
run-time estimation
resonance detection
power-noise virus mitigation
power-noise virus detection
power-noise attacks
power viruses
operating frequency
multicore microprocessors
security
Arm multicore processor
Resonant frequency
multiprocessing systems
Microprocessors
Benchmark testing
computer viruses
system-on-chip
microcontrollers
regression analysis
Metrics
pubcrawl
Resiliency
power aware computing
Scalability
biblio
Heterogenic Multi-Core System on Chip for Virtual Based Security
Submitted by aekwall on Mon, 02/10/2020 - 10:58am
multiprocessing systems
multicore computing security
virtual-based security
the GOST
standard symmetric key block cipher
neuromatrix
neural network emulation
heterogenic multicore system on chip
heterogenic multi-core system-on-chip
GOST
coding information
Cipher
virtual reality
AES
signal processing
DES
Scalability
Image Processing
assembly language
Computers
microsoft windows
Decoding
neural nets
standards
Metrics
pubcrawl
Resiliency
Kernel
system-on-chip
Hardware
encryption
Cryptography
biblio
A Security Architecture for RISC-V based IoT Devices
Submitted by aekwall on Mon, 02/10/2020 - 10:43am
small and medium-sized enterprises
RISC-V
RISC-V based IoT devices
RISC-V ISA
Scalability
scalable computing subsystem
Scalable Security
Secure Boot
secure deployment
security architecture
security concept
SIP
Resiliency
small-to-medium enterprises
SME
Software
strict power constraints
system-in-package
system-on-chip
three dimensional system-in-package
Universal Sensor Platform SoC
USeP SoC
watchdog timer
Internet of Things
authenticated watchdog timer
automation
composability
core security features
Cryptography
customizable Internet of Things platform
Device Security
embedded devices
Fraunhofer Institutes
Hardware
3D-SiP
IoT
IoT applications
IoT market
medium security level
Microelectronics Security
Monitoring
p
Predictive Metrics
pubcrawl
reduced instruction set computing
biblio
On Integrating Lightweight Encryption in Reconfigurable Scan Networks
Submitted by aekwall on Mon, 01/20/2020 - 11:01am
RSN
intellectual property
Lightweight Ciphers
lightweight stream cipher
logic testing
maintenance
malicious users
novel hardware
on-chip instrumentation
pubcrawl
PUF
reconfigurable scan networks
Resiliency
integrating lightweight encryption
Scalability
seamless integration
secret keys
Secure Wrapper
self-test
sensitive data
Software
software combined approach
system-on-chip
testing workflow
versatile software toolchain
flexible access
appropriate counter-measures
Ciphers
Cryptographic Protocols
Cryptography
data integrity
data privacy
debug modules
embedded instrumentation
embedded systems
encryption
field programmable gate arrays
-play instrument wrapper
FPGA-based implementation
Hardware
Hardware Security
IEEE standards
IEEE Std 1687
IEEE Std 1687 RSNs
IJTAG
industrial property
instrument wrapper
Instruments
integrated circuit testing
biblio
Timing Analysis for Diffie Hellman Key Exchange In U-BOOT Using Raspberry Pi
Submitted by grigby1 on Mon, 12/30/2019 - 1:18pm
telecommunication security
public key cryptography
Raspberry Pi
Raspberry-pi
Resiliency
Scalability
Secret key
security schemes
side channel attack
system-on-chip
pubcrawl
timing
Timing attack
timing attacks
timing patterns
tools
U-Boot bare metal
unsecure communication channel
word length 2048.0 bit
word length 64.0 bit
embedded systems
cryptographic
cryptographic era
Cryptographic Protocols
Cryptography
DHKE protocol
diffie hellman key exchange
Diffie Hellman Key Exchange protocol
Discrete Log Hard Problem
embedded device
brute force attacks
exponentiation
firmware
Force
GMP bignum library
Metals
modular exponentiation
networked embedded systems security
Protocols
biblio
Formal Security Verification of Concurrent Firmware in SoCs Using Instruction-Level Abstraction for Hardware*
Submitted by grigby1 on Tue, 12/17/2019 - 11:21am
resilience
Metrics
microprocessor chips
Microprogramming
multi-threading
multithreaded program verification problem
Predictive Metrics
program verification
pubcrawl
intellectual property security
Resiliency
Secure Boot design
security of data
SoC security verification
software verification techniques
system-on-chip
Systems-on-Chip
cyber-physical systems
architecture level
bit-precise reasoning
cognition
composability
Concurrency
concurrency (computers)
concurrent firmware
cyber-physical system
Access Control
firmware
firmware-visible behavior
formal security verification
Frequency modulation
Hardware
Instruction-Level Abstraction
intellectual property blocks
biblio
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers
Submitted by grigby1 on Mon, 11/04/2019 - 11:39am
NoC
Trojan horses
system-on-chip
System recovery
security attacks
security
secure routing algorithm
secret key leaking
runtime detection
Runtime
Routing
Router Systems Security
Resiliency
resilience
pubcrawl
outsourcing
network on chip security
network-on-chip architecture
network-on-chip
network routing
Multiprocessors System-on-Chip
multiprocessing systems
MPSoC
Metrics
Malicious-tolerant Routing Algorithm
malicious Hardware Trojans
logic design
invasive software
integrated circuits
hardware trojan
Hardware
biblio
ArtiFact: Architecture and CAD Flow for Efficient Formal Verification of SoC Security Policies
Submitted by aekwall on Tue, 10/22/2019 - 8:54am
security policy implementation
expensive steps
flexible infrastructure IP
functional design flow
illustrative policies
industrial SoC
integrated circuit design
modern SoC design validation
off-the-shelf formal tools
Security Engine
efficient formal verification
simulation-based security verification
SoC Security
SoC security policies
SoC Verification
streamlined verification
system-level security policies
verification time
verification tools
Security Policies Analysis
Engines
Monitoring
IP networks
system-on-chip
pubcrawl
policy-based governance
Cryptography
tools
security architecture
Complexity theory
security of data
security policy
formal verification
alternative architecture
artifact
CAD
CAD flow
centralized infrastructure IP
complex steps
critical steps
biblio
An Improved Cross-Coupled NAND Gates PUF for Bank IC Card
Submitted by grigby1 on Wed, 09/11/2019 - 1:45pm
composability
FPGA
Metrics
Microelectronics Security
physical unclonable functions
pubcrawl
resilience
Resiliency
system-on-chip
biblio
Repurposing SoC Analog Circuitry for Additional COTS Hardware Security
Submitted by grigby1 on Wed, 09/11/2019 - 1:44pm
repurposing SoC analog circuitry
Microelectronics Security
on-chip analog blocks
on-chip analog hardware blocks
physically unclonable function responses
processing algorithms
pubcrawl
PUF responses
reliable key generation
microcontrollers
resilience
Resiliency
security
Semiconductor device measurement
system-on-chip
temperature fluctuations
Temperature measurement
trusted microelectronics
Cryptography
additional COTS hardware security
analog to digital converters
analogue-digital conversion
commercial off-the-shelf system-on-a-chip integrated circuits
common COTS microcontroller
comparators
composability
COTS security
ADC
DAC
device authentication activities
digital to analog converters
digital-analogue conversion
encryption
Hardware
Hardware Security
Metrics
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