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Semiconductor device modeling

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LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment

Submitted by grigby1 on Fri, 07/29/2022 - 8:44am

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A Faster Hardware Implementation of the AES S-box

Submitted by grigby1 on Wed, 07/13/2022 - 12:12pm

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Skew-Tent Map Based CMOS Random Number Generator with Chaotic Sampling

Submitted by grigby1 on Thu, 06/30/2022 - 4:05pm

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Data-driven fault model development for superconducting logic

Submitted by grigby1 on Tue, 03/16/2021 - 1:10pm

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Analog cellular neural network for application in physical unclonable functions

Submitted by grigby1 on Thu, 04/20/2017 - 11:41am

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