Hardware

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Visible to the public TWC: Large: Collaborative: Verifiable Hardware: Chips that Prove their Own Correctness

Submitted by Abhi Shelat on Tue, 12/19/2017 - 2:47pm

This project addresses how semiconductor designers can verify the correctness of ICs that they source from possibly untrusted fabricators. Existing solutions to this problem are either based on legal and contractual obligations, or use post-fabrication IC testing, both of which are unsatisfactory or unsound. As a sound alternative, this project designs and fabricates verifiable hardware: ICs that provide proofs of their correctness for every input-output computation they perform in the field.

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Visible to the public TWC: Small: Understanding and Mitigating the Threat of a Malicious Network-on-Chip

Submitted by Koushik Chakraborty on Tue, 12/19/2017 - 2:45pm

One of the key challenges in trustworthy computing is establishing trust in the hardware layer, which is the execution platform of all software applications. Modern multiprocessor system-on-chips employ many specialized components, and scalable network-on-chips (NoC) are often deployed to efficiently connect these components. In the light of these trends, this project investigates secure and reliable computation, when the underlying NoC is compromised.

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Visible to the public TWC: Small: Quantitative Analysis and Reporting of Electromagnetic Covert and Side Channel Vulnerabilities

Submitted by Alenka Zajic on Tue, 12/19/2017 - 2:42pm

Most traditional approaches to computer security assume that information from the system can only be sent through intended output channels, such as network connection, monitor, portable disk drive, etc. Side-channel and covert-channel attacks circumvent these protections by extracting information that is leaked or deliberately sent from the system through unintended signals, such as electromagnetic emanations, power consumption, timing of computational activity, etc.

Outcomes Report URL: 
https://www.research.gov/research-portal/appmanager/base/desktop?_nfpb=true&_win...
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Visible to the public TWC: Medium: Collaborative: Computational Blinking - Computer Architecture Techniques for Mitigating Side Channels

Submitted by rck289 on Tue, 12/19/2017 - 12:40pm

Computer systems increasingly perform operations on critical and confidential data. Despite best efforts to protect this information, the side effects of computations using this data, e.g., the computation time, the power consumption, electromagnetic radiation, thermal emanations, and acoustics, can be used to decipher secret information even when it is encrypted.

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Visible to the public TWC SBE: Medium: Collaborative: Dollars for Hertz: Making Trustworthy Spectrum Sharing Technically and Economically Viable

Submitted by Jerry Park on Tue, 12/19/2017 - 12:22pm

The critical role of spectrum as a catalyst for economic growth was highlighted in the 2010 National Broadband Plan (NBP). A challenge for the NBP is realizing optimal spectrum sharing in the presence of interference caused by rogue transmissions from any source, but particularly secondary users who share the spectrum. This complex problem straddles wireless technology, industrial economics, international standards, and regulatory policy.

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Visible to the public STARSS: Small: Design of Light-weight RRAM based Hardware Security Primitives for IoT devices

Submitted by Shimeng Yu on Tue, 12/19/2017 - 11:22am

Our society has become increasingly dependent on electronic information exchange between personal devices and the cloud. Unfortunately, the number of identity and secure information leaks is on the rise. Many of the security breaches are due to insecure access channels to the cloud. The security problem is likely to be exacerbated in the Internet-of-Things (IoT) era where billions of devices in our homes, offices and cars are digitally connected.

Outcomes Report URL: 
https://www.research.gov/research-portal/appmanager/base/desktop?_nfpb=true&_win...
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Visible to the public SaTC: Collaborative: Exploiting Spintronics for Security, Trust and Authentication

Submitted by Rashmi Jha on Tue, 12/19/2017 - 10:35am

The Complementary Metal Oxide Semiconductor (CMOS) based security primitives typically suffer from area/power overhead, sensitivity to environmental fluctuations and limited randomness and entropy offered by Silicon substrate. Spintronic circuits can complement the existing CMOS based security and trust infrastructures. This project explores ways to uncover the security specific properties of the magnetic nanowire and capture them in detailed circuit model.

Outcomes Report URL: 
https://www.research.gov/research-portal/appmanager/base/desktop?_nfpb=true&_win...
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Visible to the public SaTC: Collaborative: Exploiting Spintronics for Security, Trust and Authentication

Submitted by Rashmi Jha on Tue, 12/19/2017 - 10:33am

The Complementary Metal Oxide Semiconductor (CMOS) based security primitives typically suffer from area/power overhead, sensitivity to environmental fluctuations and limited randomness and entropy offered by Silicon substrate. Spintronic circuits can complement the existing CMOS based security and trust infrastructures. This project explores ways to uncover the security specific properties of the magnetic nanowire and capture them in detailed circuit model.

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Visible to the public SaTC: Collaborative: Exploiting Spintronics for Security, Trust and Authentication

Submitted by Swaroop Ghosh on Tue, 12/19/2017 - 10:11am

The Complementary Metal Oxide Semiconductor (CMOS) based security primitives typically suffer from area/power overhead, sensitivity to environmental fluctuations and limited randomness and entropy offered by Silicon substrate. Spintronic circuits can complement the existing CMOS based security and trust infrastructures. This project explores ways to uncover the security specific properties of the magnetic nanowire and capture them in detailed circuit model.

Outcomes Report URL: 
https://www.research.gov/research-portal/appmanager/base/desktop?_nfpb=true&_win...
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Visible to the public  SaTC: Collaborative: Exploiting Spintronics for Security, Trust and Authentication

Submitted by Swaroop Ghosh on Tue, 12/19/2017 - 10:10am

The Complementary Metal Oxide Semiconductor (CMOS) based security primitives typically suffer from area/power overhead, sensitivity to environmental fluctuations and limited randomness and entropy offered by Silicon substrate. Spintronic circuits can complement the existing CMOS based security and trust infrastructures. This project explores ways to uncover the security specific properties of the magnetic nanowire and capture them in detailed circuit model.