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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
CMOS logic circuits
biblio
Automated Synthesis of Differential Power Attack Resistant Integrated Circuits
Submitted by aekwall on Mon, 08/24/2020 - 12:41pm
Dynamic Differential Logic
cryptographic processors
cryptographic systems
differential circuit design
differential logic
Differential Power Analysis
differential power analysis attacks
differential power attack resistant integrated circuits
DPA attack resistance
DPA resistant cell designs
combinational cells
fully automated synthesis system DPA resistant integrated circuits
MDPL
multiplying circuits
RT level Verilog specifications
secret key information
Secure Differential Multiplexer Logic
sequential cells
sequential circuits
power consumption
Resiliency
pubcrawl
composability
Cryptography
standards
tools
Libraries
Automated Response Actions
Logic gates
private key cryptography
Power demand
logic design
Hardware Security
Resistance
combinational circuits
Automated Synthesis
CMOS logic circuits
CMOS synthesis
biblio
Fully integrable current-mode feedback suppressor as an analog countermeasure against CPA attacks in 40nm CMOS technology
Submitted by grigby1 on Wed, 02/21/2018 - 1:41pm
Power demand
Logic gates
Metrics
Microelectronic Security
MTD improvement
on-chip analog-level CPA countermeasure
Power Analysis Attack
power aware computing
power consumption
IoT
pubcrawl
resilience
Resiliency
sensible data security
side channel attack
size 40 nm
system-on-chip
ultraconstrained IoT smart devices
CPA
circuit feedback
CMOS
CMOS analogue integrated circuits
CMOS logic circuits
CMOS technology
composability
correlation coefficient
correlation power analysis
Analog-level
CPA attacks
CPA-resistant cryptographic devices
Cryptography
current-mode
current-mode circuits
data-dependency
fully integrable current-mode feedback suppressor
Internet of Things
biblio
Linear regression based multi-state logic decomposition approach for efficient hardware implementation
Submitted by grigby1 on Thu, 12/28/2017 - 1:17pm
pattern matching
multi-valued logic
multistate logic decomposition approach
multivalued logic
multivalued logic circuits
multivalued minterms
MVL decomposition
nanoelectronics
Nanoscale devices
more-than-Moore scaling
polynomials
pubcrawl
quaternary sum circuit
regression analysis
technology mapping
visual pattern matching
word length 4 bit
decision diagrams
binary CMOS
binary switches
CMOS adder
CMOS logic circuits
complex polynomials
Compositionality
data conversion
data science
adders
decomposition
domain selection
efficient hardware implementation
interconnection requirements
linear regression
logic design
Metrics
