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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
digital signal processor
biblio
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
Submitted by aekwall on Mon, 11/09/2020 - 1:41pm
low-overhead robust RTL signature
FIR filters
IP piracy
flip-flops
covert signature embedding process
digital signal processor
DSP core protection
DSP-MP IP core
IP vendors
FIR filter
Multimedia Processor
nonsignature FIR RTL design
register-transfer level
reusable Intellectual Property cores
robust IP owner
secured smart CE device
smart CE design
smart Consumer Electronics devices
Registers
Hardware
Resiliency
pubcrawl
composability
policy-based governance
digital signatures
microprocessor chips
Multiplexing
IP networks
digital signal processing chips
Finite impulse response filters
adders
logic circuits
logic design
Latches
Consumer electronics
biblio
Distributed Osmotic Computing Approach to Implementation of Explainable Predictive Deep Learning at Industrial IoT Network Edges with Real-Time Adaptive Wavelet Graphs
Submitted by grigby1 on Mon, 12/10/2018 - 11:41am
osmotic microservice
graph-based approach
IIoT network fog layer
IIoT systems
Industrial IoT
industrial IoT network edges
IoT development costs
large scale industrial Internet of Things
Logic gates
low-level machine language
LSTM networks
network cloud layer
graph theory
real-time
real-time adaptive wavelet graphs
real-time DSP
real-time graph-based Coiflet wavelets
real-time systems
system complexities
wavelet analysis
Wavelet Graph
wavelet transforms
XAI deep learning pre-processing applications
deep learning
Internet of Things
resilience
pubcrawl
Resiliency
Scalability
Hardware
xai
learning (artificial intelligence)
artificial intelligence deep learning problem
communication network noise
data quality
Cloud Computing
delay time
delays
digital signal processing chips
digital signal processor
distributed computing
distributed edge computing
distributed osmotic computing approach
distributed processing
edge layer
explainable artificial intelligence
