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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Program processors
biblio
Security approaches for data aggregation in Wireless Sensor Networks against Sybil Attack
Submitted by aekwall on Mon, 02/18/2019 - 11:57am
data aggregation
Metrics
sybil attacks
wireless sensor networks
Wireless Sensor Network
Routing protocols
misbehavior detection parameters
magnetic sensors
fair resourse allocation
detection techniques
telecommunication security
biosensors
batteries
Attacker node
Sybil attack
composability
pubcrawl
Program processors
security
biblio
LiteHAX: Lightweight Hardware-Assisted Attestation of Program Execution
Submitted by aekwall on Wed, 02/13/2019 - 10:58am
Runtime
programming
pubcrawl
RA
reduced instruction set computing
remote device integrity
Resiliency
RISC-based embedded devices
RISC-V system-on-chip
Program processors
runtime attestation
security
security of data
security service
SoC
software binaries
system-on-chip
Trusted Computing
embedded Internet of Things devices
composability
control-flow attacks
control-flow attestation schemes
data flow computing
data integrity
data-flow events
data-oriented programming
DOP attacks
attestation
embedded systems
hardware-assisted remote attestation scheme
Human behavior
Internet of Things
lightweight hardware-assisted attestation of program execution
LiteHAX
malicious modification
malware
biblio
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
Submitted by grigby1 on Wed, 09/12/2018 - 10:25am
SIMD
Program processors
Programmable SoC
pubcrawl
real-time on-line pattern search
real-time systems
resilience
Resiliency
Scalability
search problems
platform based design methodologies
string matching
system monitoring
system-on-chip
SystemC
TCP
TCP packets
Xilinx Zynq programmable SoC
Zynq
High-Le'vel Synthesis
Algorithm design and analysis
BM string search algorithm
Boyer-Moore
Boyer-Moore algorithm
computer network security
deep packet inspection
FPGA
Hardware
high level synthesis
Accelerator
high-level synthesis
Inspection
MISD parallelism
Network Monitoring
network security
parallel processing
Payloads
Platform Based Design
biblio
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with \#x003E;0.1 timing error rate tolerance for IoT applications
Submitted by grigby1 on Thu, 06/07/2018 - 2:07pm
Internet of Things
VDD scaling
timing error rate tolerance
timing
Throughput
system-on-chip
sign-magnitude number format
Resiliency
resilience
Razor timing violation detection
pubcrawl
programmable FC-DNN accelerator design
Program processors
Neural Network Resilience
neural nets
IoT applications
1.2GHz 568nJ/prediction sparse deep-neural-network engine
frequency 667 MHz
frequency 1.2 GHz
frequency 1 GHz
FCLK scaling
Error analysis
Engines
Energy Efficiency
datapath logic
data sparsity
circuit-level timing violation tolerance
circuit resilience
algorithmic resilience
algorithmic error tolerance
aggregate timing violation rates
28nm SoC
biblio
Automotive Cyber #x2013;Physical Systems: A Tutorial Introduction
Submitted by el_wehby on Fri, 05/25/2018 - 3:22pm
Algorithm design and analysis
Automotive engineering
computer architecture
Control Theory
Program processors
Software algorithms
Tutorials
1553757
biblio
Acceleration of RSA processes based on hybrid ARM-FPGA cluster
Submitted by grigby1 on Wed, 02/21/2018 - 12:38pm
resilience
MPI
Multicore Computing
multicore computing security
multicore desktop
multiprocessing systems
node-to-node communication
none-subtraction Montgomery algorithm
Program processors
pubcrawl
public key cryptography
microprocessor chips
Resiliency
RSA
RSA algorithm
RSA processes acceleration
Scalability
software-hardware cooperation
system-on-chip
Xilinx Zynq SoC
Zynq
FPGA fabric
Algorithm design and analysis
ARM CPU
Chinese remainder theorem
cluster
cluster infrastructure
Clustering algorithms
computer architecture
CRT
field programmable gate arrays
Acceleration
Hardware
Heterogeneous
hybrid architectures
hybrid ARM-FPGA cluster
Intel i7-3770
many-core server
message passing
message passing interface
Metrics
biblio
Hermes: Secure heterogeneous multicore architecture design
Submitted by grigby1 on Wed, 02/21/2018 - 12:37pm
Program processors
trust-aware routing algorithm
tenant security
system-on-chip
system-level integration
SoC design
security
secure heterogeneous multicore architecture design
secure cores
Scalability
Resiliency
resilience
pubcrawl
programmable secure router interface
programmable RISC cores
programmable distributed group key management scheme
accelerator function units
nonsecure cores
multiprocessing systems
multiple processing elements
multilevel user-defined security
Multicore processing
multicore computing security
Multicore Computing
Metrics
Hermes architecture
Hardware
general-purpose system-on-chip architectures
DSP
ASIC
application executable code
biblio
Confidentiality and Authenticity in a Platform Based on Network-on-Chip
Submitted by grigby1 on Wed, 02/21/2018 - 12:37pm
network performance
SoCIN-based systems
silicon overhead
Security Properties
security mechanisms
security aspects
security
Scalability
Resiliency
resilience
reference multicore platform
pubcrawl
Program processors
processing elements
networks-on-chip
network-on-chip
advanced encryption standard
network level
Network interfaces
multiprocessing systems
multicore computing security
Multicore Computing
Metrics
Many-core systems
low-cost interconnect architecture
encryption
Cryptography
confidentiality
computer architecture
authenticity
AES model
biblio
Optimizing Task Assignment with Minimum Cost on Heterogeneous Embedded Multicore Systems Considering Time Constraint
Submitted by grigby1 on Wed, 02/21/2018 - 12:37pm
Processor scheduling
Guaranteed Probability
Heterogeneous Embedded Multicore System
heterogeneous embedded multicore systems
heterogeneous multicore architectures
minimum cost
multiprocessing systems
optimal energy efficiency
optimizing task heterogeneous assignment with probability algorithm
OTHAP
processor and voltage assignment with probability problem
execution time
processor scheduling algorithm
PVAP problem
real-time embedded systems
system performance model
Task Assignment
task assignment optimization
task completion probability
time constraint
multicore computing security
Multicore Computing
Program processors
pubcrawl
Scalability
Algorithm design and analysis
energy consumption
real-time systems
Reliability
directed graphs
probability
Metrics
Signal processing algorithms
resilience
embedded systems
Resiliency
battery-based embedded systems
computer systems
DAG
data-dependent aperiodic tasks
directed acyclic graph
dynamic programming
dynamic programming algorithm
Energy Efficiency
biblio
Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing
Submitted by K_Hooper on Wed, 02/14/2018 - 10:59am
Artificial Intelligence
artificial intelligence security
Artificial Neural Networks
Energy Efficiency
Human behavior
Metrics
Nonvolatile memory
Program processors
pubcrawl
Random access memory
Resiliency
Scalability
security
Very large scale integration
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