On Integrating Lightweight Encryption in Reconfigurable Scan Networks
Title | On Integrating Lightweight Encryption in Reconfigurable Scan Networks |
Publication Type | Conference Paper |
Year of Publication | 2019 |
Authors | Thiemann, Benjamin, Feiten, Linus, Raiola, Pascal, Becker, Bernd, Sauer, Matthias |
Conference Name | 2019 IEEE European Test Symposium (ETS) |
Date Published | may |
Keywords | -play instrument wrapper, appropriate counter-measures, Ciphers, cryptographic protocols, cryptography, data integrity, data privacy, debug modules, embedded instrumentation, Embedded systems, Encryption, field programmable gate arrays, flexible access, FPGA-based implementation, Hardware, hardware security, IEEE standards, IEEE Std 1687, IEEE Std 1687 RSNs, IJTAG, industrial property, instrument wrapper, Instruments, integrated circuit testing, integrating lightweight encryption, intellectual property, Lightweight Ciphers, lightweight stream cipher, logic testing, maintenance, malicious users, novel hardware, on-chip instrumentation, pubcrawl, PUF, reconfigurable scan networks, Resiliency, RSN, Scalability, seamless integration, secret keys, Secure Wrapper, self-test, sensitive data, Software, software combined approach, system-on-chip, testing workflow, versatile software toolchain |
Abstract | Reconfigurable Scan Networks (RSNs) are a powerful tool for testing and maintenance of embedded systems, since they allow for flexible access to on-chip instrumentation such as built-in self-test and debug modules. RSNs, however, can be also exploited by malicious users as a side-channel in order to gain information about sensitive data or intellectual property and to recover secret keys. Hence, implementing appropriate counter-measures to secure the access to and data integrity of embedded instrumentation is of high importance. In this paper we present a novel hardware and software combined approach to ensure data privacy in IEEE Std 1687 (IJTAG) RSNs. To do so, both a secure IJTAG compliant plug-and-play instrument wrapper and a versatile software toolchain are introduced. The wrapper demonstrates the necessary architectural adaptations required when using a lightweight stream cipher, whereas the software toolchain provides a seamless integration of the testing workflow with stream cipher. The applicability of the method is demonstrated by an FPGA-based implementation. We report on the performance of the developed instrument wrapper, which is empirically shown to have only a small impact on the workflow in terms of hardware overhead, operational costs and test time overhead. |
DOI | 10.1109/ETS.2019.8791543 |
Citation Key | thiemann_integrating_2019 |
- RSN
- intellectual property
- Lightweight Ciphers
- lightweight stream cipher
- logic testing
- maintenance
- malicious users
- novel hardware
- on-chip instrumentation
- pubcrawl
- PUF
- reconfigurable scan networks
- Resiliency
- integrating lightweight encryption
- Scalability
- seamless integration
- secret keys
- Secure Wrapper
- self-test
- sensitive data
- Software
- software combined approach
- system-on-chip
- testing workflow
- versatile software toolchain
- flexible access
- appropriate counter-measures
- Ciphers
- Cryptographic Protocols
- Cryptography
- data integrity
- data privacy
- debug modules
- embedded instrumentation
- embedded systems
- encryption
- field programmable gate arrays
- -play instrument wrapper
- FPGA-based implementation
- Hardware
- Hardware Security
- IEEE standards
- IEEE Std 1687
- IEEE Std 1687 RSNs
- IJTAG
- industrial property
- instrument wrapper
- Instruments
- integrated circuit testing