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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
logic testing
biblio
On Integrating Lightweight Encryption in Reconfigurable Scan Networks
Submitted by aekwall on Mon, 01/20/2020 - 11:01am
RSN
intellectual property
Lightweight Ciphers
lightweight stream cipher
logic testing
maintenance
malicious users
novel hardware
on-chip instrumentation
pubcrawl
PUF
reconfigurable scan networks
Resiliency
integrating lightweight encryption
Scalability
seamless integration
secret keys
Secure Wrapper
self-test
sensitive data
Software
software combined approach
system-on-chip
testing workflow
versatile software toolchain
flexible access
appropriate counter-measures
Ciphers
Cryptographic Protocols
Cryptography
data integrity
data privacy
debug modules
embedded instrumentation
embedded systems
encryption
field programmable gate arrays
-play instrument wrapper
FPGA-based implementation
Hardware
Hardware Security
IEEE standards
IEEE Std 1687
IEEE Std 1687 RSNs
IJTAG
industrial property
instrument wrapper
Instruments
integrated circuit testing
biblio
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection
Submitted by grigby1 on Wed, 04/11/2018 - 1:59pm
Sensitivity
logic testing
Power based Side-channel
Power measurement
probability
process variation levels
Process Variations
pubcrawl
relative power difference
resilience
Resiliency
logic circuits
sequential type Trojans
side channel analysis
spatial correlation
Systematics
test pattern generation
Trojan activation probability
trojan horse detection
Trojan horses
Trojan inserted circuits
hardware trojan
automatic test pattern generation
combinational type Trojans
composability
cyber physical systems
delays
Detection sensitivity
efficient Trojan detection approach
elevated process variations
Hardware
AES-128 circuit
hardware Trojan detection
high detection sensitivity
integrated circuit design
integrated circuit testing
integrated circuits
intra-die-variation
invasive software
ISCAS 89 benchmark
ITC 99 benchmark
biblio
Hardware malicious circuit identification using self referencing approach
Submitted by grigby1 on Wed, 02/21/2018 - 12:41pm
post-silicon testing
Trojan horses
testing
Test vector generation
Temporal Self Referencing
side channel analysis
sequential Trojans
Sequential trojan
self referencing approach
security vulnerabilities
Robust Trojans
Resiliency
resilience
pubcrawl
Power measurement
composability
Payloads
outsourced products
Microelectronic Security
Metrics
malicious inclusions
logic testing
leakage power
invasive software
hardware Trojan detection sensitivity
hardware malicious circuit identification
Hardware
delays
Cryptography
biblio
Slack removal for enhanced reliability and trust
Submitted by BrandonB on Wed, 05/06/2015 - 10:34am
Small Delay Defects
mission-critical application
pattern count
reliability enhancement
security of data
security vulnerabilities
security-critical application
slack removal
Slacks
malicious circuitries
test quality
testing
timing slacks
transition fault patterns
Trojan horses
trust enhancement
Wires
fabrication
care bit density intact
Circuit faults
delay defect detection
delay defects
delay unit insertion
delays
design for testability
design technique
At-speed Testing
Hardware
hardware trojan
Hardware Trojans
integrated circuit reliability
logic circuits
Logic gates
logic testing
