| Title | A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Lian, Mengyun, Wang, Jian, Lu, Jinzhi |
| Conference Name | 2018 Eighth International Conference on Instrumentation Measurement, Computer, Communication and Control (IMCCC) |
| Keywords | benchmark test set, communication performance optimization, defense strategies, Integrated circuit interconnections, inter-core interconnection method, invasive software, logic circuits, manufacturing processes, Metrics, multiprocessing systems, multiprocessor chip security, network on chip security, network throughput reduction, network-on-chip, new hardware logic circuit, NoC, NoC hardware security, NoC power consumption, NoC vulnerability, on-chip systems, pubcrawl, replay-type hardware Trojan, research hotspots, resilience, Resiliency, Scalability |
| Abstract | NoC (Network-on-Chip) is widely considered and researched by academic communities as a new inter-core interconnection method that replaces the bus. Nowadays, the complexity of on-chip systems is increasing, requiring better communication performance and scalability. Therefore, the optimization of communication performance has become one of the research hotspots. While the NoC is rapidly developing, it is threatened by hardware Trojans inserted during the design or manufacturing processes. This leads to that the attackers can exploit NoC's vulnerability to attack the on-chip systems. To solve the problem, we design and implement a replay-type hardware Trojan inserted into the NoC, aiming to provide a benchmark test set to promote the defense strategies for NoC hardware security. The experiment proves that the power consumption of the designed Trojan accounts for less than one thousandth of the entire NoC power consumption and area. Besides, simulation experiments reveal that this replaytype hardware Trojan can reduce the network throughput. |
| DOI | 10.1109/IMCCC.2018.00324 |
| Citation Key | lian_new_2018 |
A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security