Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs
| Title | Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | León, Raquel, Domínguez, Adrián, Carballo, Pedro P., Núñez, Antonio |
| Conference Name | 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS) |
| Publisher | IEEE |
| ISBN Number | 978-1-7281-5458-9 |
| Keywords | Computer architecture, CPU-DMA based architecture, deep packet inspection, ESL, field programmable gate arrays, Hardware, hardware accelerators, hardware-IP based architecture, hybrid CPU/FPGA, Inspection, logic design, Mentor Vista, pubcrawl, resilience, Resiliency, Scalability, search engines, Software, system on chip, system-on-chip, system-on-chip FPGA, time-domain analysis, time-varying systems, TLM, transaction level modeling, virtual platform, virtual platforms |
| Abstract | Virtual platforms provide a full hardware/software platform to study device limitations in an early stages of the design flow and to develop software without requiring a physical implementation. This paper describes the development process of a virtual platform for Deep Packet Inspection (DPI) hardware accelerators by using Transaction Level Modeling (TLM). We propose two DPI architectures oriented to System-on-Chip FPGA. The first architecture, CPU-DMA based architecture, is a hybrid CPU/FPGA where the packets are filtered in the software domain. The second architecture, Hardware-IP based architecture, is mainly implemented in the hardware domain. We have created two virtual platforms and performed the simulation, the debugging and the analysis of the hardware/software features, in order to compare results for both architectures. |
| URL | https://ieeexplore.ieee.org/document/8959882 |
| DOI | 10.1109/DCIS201949030.2019.8959882 |
| Citation Key | leon_deep_2019 |
- resilience
- virtual platforms
- virtual platform
- transaction level modeling
- TLM
- time-varying systems
- time-domain analysis
- system-on-chip FPGA
- system-on-chip
- system on chip
- Software
- search engines
- Scalability
- Resiliency
- computer architecture
- pubcrawl
- Mentor Vista
- logic design
- Inspection
- hybrid CPU/FPGA
- hardware-IP based architecture
- hardware accelerators
- Hardware
- field programmable gate arrays
- ESL
- deep packet inspection
- CPU-DMA based architecture