| Title | Customized Locking of IP Blocks on a Multi-Million-Gate SoC |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Sengupta, A., Ashraf, M., Nabeel, M., Sinanoglu, O. |
| Conference Name | 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) |
| Date Published | nov |
| Keywords | composability, Erbium, Hardware, industrial designs, industrial property, integrated circuit design, integrated circuit manufacture, integrated circuits, IP block, IP networks, IP piracy, logic design, Logic gates, logic locking, multimillion-gate SoC, multiple IP blocks, off-site untrusted fabrication facilities, policy-based governance, pubcrawl, Resiliency, security, Solid modeling, system-on-chip, VLSI testing |
| Abstract | Reliance on off-site untrusted fabrication facilities has given rise to several threats such as intellectual property (IP) piracy, overbuilding and hardware Trojans. Logic locking is a promising defense technique against such malicious activities that is effected at the silicon layer. Over the past decade, several logic locking defenses and attacks have been presented, thereby, enhancing the state-of-the-art. Nevertheless, there has been little research aiming to demonstrate the applicability of logic locking with large-scale multi-million-gate industrial designs consisting of multiple IP blocks with different security requirements. In this work, we take on this challenge to successfully lock a multi-million-gate system-on-chip (SoC) provided by DARPA by taking it all the way to GDSII layout. We analyze how specific features, constraints, and security requirements of an IP block can be leveraged to lock its functionality in the most appropriate way. We show that the blocks of an SoC can be locked in a customized manner at 0.5%, 15.3%, and 1.5% chip-level overhead in power, performance, and area, respectively. |
| DOI | 10.1145/3240765.3243467 |
| Citation Key | sengupta_customized_2018 |
Customized Locking of IP Blocks on a Multi-Million-Gate SoC