Diagnosis of multiple faults with highly compacted test responses
| Title | Diagnosis of multiple faults with highly compacted test responses |
| Publication Type | Conference Paper |
| Year of Publication | 2014 |
| Authors | Cook, A., Wunderlich, H.-J. |
| Conference Name | Test Symposium (ETS), 2014 19th IEEE European |
| Date Published | May |
| Keywords | Accuracy, built-in self test, built-in self-test, Circuit faults, compacted test responses, Compaction, compressed test responses, defects cluster, Diagnosis, embedded test, Equations, fault diagnosis, faulty signatures, field return analysis, integrated circuit testing, integrated circuit yield, linear properties, logic diagnosis, Mathematical model, MISR compactor, multiple fault diagnosis, multiple fault probability, Multiple Faults, probability, process learning, Response Compaction, yield ramp-up |
| Abstract | Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios. |
| DOI | 10.1109/ETS.2014.6847796 |
| Citation Key | 6847796 |
- field return analysis
- yield ramp-up
- Response Compaction
- process learning
- probability
- Multiple Faults
- multiple fault probability
- multiple fault diagnosis
- MISR compactor
- Mathematical model
- logic diagnosis
- linear properties
- integrated circuit yield
- integrated circuit testing
- Accuracy
- faulty signatures
- fault diagnosis
- Equations
- embedded test
- Diagnosis
- defects cluster
- compressed test responses
- Compaction
- compacted test responses
- Circuit faults
- built-in self-test
- built-in self test