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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
benchmark circuits
biblio
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access
Submitted by aekwall on Tue, 09/08/2020 - 9:59am
locked circuits
Chained Attacks
working chip
unauthorized scan access
secret key recovery
scan chain
SAT attack
robust DFS technique
robust DFS design
robust design-for-security architecture
restricted scan chain access
logic locking security
logic locking attacks
Scalability
IP piracy
Boolean satisfiability based attack
benchmark circuits
ATPG
Boolean functions
logic circuits
computability
Security analysis
logic locking
pubcrawl
Resiliency
Cryptography
biblio
On the Impossibility of Approximation-Resilient Circuit Locking
Submitted by grigby1 on Thu, 03/12/2020 - 12:02pm
IC
signature based defense
security guarantees
Scalability
Resiliency
resilience
relaxed notion
pubcrawl
original circuit
microscopy
malicious foundry
long-standing hardness assumptions
logic locking
learning (artificial intelligence)
Integrated circuit modeling
Integrated Circuit Camouflaging
Adversary Models
Foundries
formally defined notions
formal approach
exponentially approximation-resilient
exact-recovery-resiliency
digital signatures
Cryptography
Computational modeling
cL
Boolean functions
boolean circuits
benchmark circuits
approximation-resilient Circuit locking
approximation-resiliency
algorithmic attacks
biblio
Hardware trojan detection by symmetry breaking in path delays
Submitted by BrandonB on Wed, 05/06/2015 - 11:33am
inter-and intra-die variations
Trojan horses
Transistors
symmetry breaking
symmetric paths
subcircuit consistencies
side channel methods
Sensitivity
path delays
path delay
Logic gates
invasive software
benchmark circuits
integrated circuits
IC
HT
hardware Trojan detection
hardware trojan
Hardware
electronic engineering computing
detect modifications
delays
circuit symmetries
