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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Hardware
biblio
Heterogenic Multi-Core System on Chip for Virtual Based Security
Submitted by aekwall on Mon, 02/10/2020 - 11:58am
multiprocessing systems
multicore computing security
virtual-based security
the GOST
standard symmetric key block cipher
neuromatrix
neural network emulation
heterogenic multicore system on chip
heterogenic multi-core system-on-chip
GOST
coding information
Cipher
virtual reality
AES
signal processing
DES
Scalability
Image Processing
assembly language
Computers
microsoft windows
Decoding
neural nets
standards
Metrics
pubcrawl
Resiliency
Kernel
system-on-chip
Hardware
encryption
Cryptography
biblio
Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application
Submitted by aekwall on Mon, 02/10/2020 - 11:44am
piccolo encryption algorithm
4 input LUTs
64 bits block size
area optimization
ASIC
constrained RFID application
different design strategies
efficient hardware architecture
Fiestel structure
hardware design
hardware metrics
low resource applications
optimized area
Piccolo Algorithm
128 bits
piccolo lightweight algorithm
radiofrequency identification
relevant lightweight block ciphers
severe security concerns
supports high speed
Throughput.
tremendous pace
ultra-lightweight applications
variable key size
word length 64.0 bit
word length 80.0 bit
Xillinx
Microelectronics Security
security applications
field programmable gate arrays
FPGA
Cryptography
encryption
Internet of Things
telecommunication security
Hardware
Table lookup
IoT applications
smart devices
Resiliency
pubcrawl
composability
IoT
RFID
Throughput
Ciphers
security issues
Predictive Metrics
private information
word length 128.0 bit
Hardware Implementation
hardware resources
lightweight cryptographic algorithms
S-box
lightweight cryptography
biblio
A New Information Extractor for Profiled DPA and Implementation of High Order Masking Circuit
Submitted by aekwall on Mon, 02/10/2020 - 11:44am
extracting information
Microelectronics Security
time reduction
space reduction
side channel attack
security circuit implementation
profiled stage
profiled DPA
new information extractor
machine learning method
information retrieval
high order masking scheme
high order masking circuit
high order masking
Cryptography
explained local variance
ELV
CHES 2015
Predictive Metrics
computer science
principal component analysis
microsoft windows
Data mining
composability
pubcrawl
Resiliency
learning (artificial intelligence)
Hardware
biblio
Hardware Trojan Detection Combine with Machine Learning: an SVM-based Detection Approach
Submitted by aekwall on Mon, 02/10/2020 - 11:43am
Predictive Metrics
Microelectronics Security
Xilinx SPARTAN-6
Trojan detection rate
Trojan detection
SVM-based detection approach
support vector machine classifier
support vector machine (SVM)
side-channel analysis (SCA)
side-channel analysis
SAKURA-G circuit board
IC
hardware Trojan detection
hardware trojan
security
integrated circuits
Trojan horses
Training
composability
pubcrawl
Resiliency
machine learning
learning (artificial intelligence)
Support vector machines
invasive software
Kernel
Hardware
field programmable gate arrays
biblio
A Security Architecture for RISC-V based IoT Devices
Submitted by aekwall on Mon, 02/10/2020 - 11:43am
small and medium-sized enterprises
RISC-V
RISC-V based IoT devices
RISC-V ISA
Scalability
scalable computing subsystem
Scalable Security
Secure Boot
secure deployment
security architecture
security concept
SIP
Resiliency
small-to-medium enterprises
SME
Software
strict power constraints
system-in-package
system-on-chip
three dimensional system-in-package
Universal Sensor Platform SoC
USeP SoC
watchdog timer
Internet of Things
authenticated watchdog timer
automation
composability
core security features
Cryptography
customizable Internet of Things platform
Device Security
embedded devices
Fraunhofer Institutes
Hardware
3D-SiP
IoT
IoT applications
IoT market
medium security level
Microelectronics Security
Monitoring
p
Predictive Metrics
pubcrawl
reduced instruction set computing
biblio
Use of Machine Learning in Detecting Network Security of Edge Computing System
Submitted by grigby1 on Tue, 01/28/2020 - 2:38pm
machine learning
Training
Support vector machines
support vector machine
Smart homes
smart home system
Resiliency
resilience
RBF-function SVM method
radial basis function networks
pubcrawl
privacy
network security detection
mutation code detection
Alibaba ECS
learning (artificial intelligence)
IoT systems
Internet of Things
home automation
Hardware
feature extraction
edge computing system
edge computing
computer network security
composability
code mutation
Cloud Computing
biblio
Zero Knowledge Authentication for Reuse of IPs in Reconfigurable Platforms
Submitted by aekwall on Mon, 01/20/2020 - 12:13pm
field programmable gate arrays
Scalability
Hardware
Resiliency
pubcrawl
policy-based governance
Watermarking
authentication
delays
Human Factors
zero knowledge proof
field programmable gate array
intellectual property
zero trust
biblio
Power-Grid Controller Anomaly Detection with Enhanced Temporal Deep Learning
Submitted by aekwall on Mon, 01/20/2020 - 12:12pm
power-grid controller anomaly detection
control engineering computing
LSTM
actuators
data-driven defense system
enhanced temporal deep learning
Hardware Performance Counter
Kolmogorov–Smirnov test
power-grid controller
Human Factors
power-grid system
programmable logic controller
security-critical cyber-physical systems
temporal deep learning detection
temporal deep learning model
time 360.0 ms
zero trust
Scalability
deep learning
sensors
process control
power grids
power system security
power engineering computing
Zero-day attacks
Substations
policy-based governance
pubcrawl
Resiliency
learning (artificial intelligence)
invasive software
malware
Hardware
biblio
On Integrating Lightweight Encryption in Reconfigurable Scan Networks
Submitted by aekwall on Mon, 01/20/2020 - 12:01pm
RSN
intellectual property
Lightweight Ciphers
lightweight stream cipher
logic testing
maintenance
malicious users
novel hardware
on-chip instrumentation
pubcrawl
PUF
reconfigurable scan networks
Resiliency
integrating lightweight encryption
Scalability
seamless integration
secret keys
Secure Wrapper
self-test
sensitive data
Software
software combined approach
system-on-chip
testing workflow
versatile software toolchain
flexible access
appropriate counter-measures
Ciphers
Cryptographic Protocols
Cryptography
data integrity
data privacy
debug modules
embedded instrumentation
embedded systems
encryption
field programmable gate arrays
-play instrument wrapper
FPGA-based implementation
Hardware
Hardware Security
IEEE standards
IEEE Std 1687
IEEE Std 1687 RSNs
IJTAG
industrial property
instrument wrapper
Instruments
integrated circuit testing
biblio
Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support
Submitted by aekwall on Mon, 01/20/2020 - 12:00pm
Hardware
tools
security-critical hardware implementations
Scalability
Resiliency
pubcrawl
Post /Pre silicon analysis
multiple fault injection support
Mathematical model
Lightweight Ciphers
lightweight block ciphers
Integrated circuit modeling
idealized fault models
hardware-oriented structural cipher descriptions
hardware-oriented framework
hardware-oriented algebraic fault attack framework
actual implementation
framework
field-programmable gate array platform
field programmable gate arrays
fault injector
Fault injction attack
Cryptography
conjunctive normal form clauses
Circuit faults
Ciphers
cipher implementations
Cipher
Analytical models
algebraic fault attack tool
algebraic equations
algebra
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