| Title | Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Ramu, Gandu, Mishra, Zeesha, Acharya, B. |
| Conference Name | 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON) |
| Date Published | mar |
| Keywords | 128 bits, 4 input LUTs, 64 bits block size, area optimization, ASIC, Ciphers, composability, constrained RFID application, cryptography, different design strategies, efficient hardware architecture, Encryption, field programmable gate arrays, Fiestel structure, FPGA, Hardware, hardware design, Hardware Implementation, hardware metrics, hardware resources, Internet of Things, IoT, IoT applications, lightweight cryptographic algorithms, lightweight cryptography, low resource applications, Microelectronics Security, optimized area, Piccolo Algorithm, piccolo encryption algorithm, piccolo lightweight algorithm, Predictive Metrics, private information, pubcrawl, radiofrequency identification, relevant lightweight block ciphers, Resiliency, RFID, S-box, security applications, security issues, severe security concerns, smart devices, supports high speed, Table lookup, telecommunication security, Throughput, Throughput., tremendous pace, ultra-lightweight applications, variable key size, word length 128.0 bit, word length 64.0 bit, word length 80.0 bit, Xillinx |
| Abstract | The deployment of smart devices in IoT applications are increasing with tremendous pace causing severe security concerns, as it trade most of private information. To counter that security issues in low resource applications, lightweight cryptographic algorithms have been introduced in recent past. In this paper we propose efficient hardware architecture of piccolo lightweight algorithm uses 64 bits block size with variable key size of length 80 and 128 bits. This paper introduces novel hardware architecture of piccolo-80, to supports high speed RFID security applications. Different design strategies are there to optimize the hardware metrics trade-off for particular application. The algorithm is implemented on different family of FPGAs with different devices to analyze the performance of design in 4 input LUTs and 6 input LUTs implementations. In addition, the results of hardware design are evaluated and compared with the most relevant lightweight block ciphers, shows the proposed architecture finds its utilization in terms of speed and area optimization from the hardware resources. The increment in throughput with optimized area of this architecture suggests that piccolo can applicable to implement for ultra-lightweight applications also. |
| DOI | 10.1109/IEMECONX.2019.8877071 |
| Citation Key | ramu_hardware_2019 |
Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application