field programmable gate arrays

biblio

FPGA Bitstream Security: A Day in the Life

Submitted by grigby1 on Mon, 11/02/2020 - 11:29am

IPS
system-on-chip platforms
system-on-chip
system integrator
SoC platform
security concerns
security
Resiliency
resilience
reconfigurable architectures
pubcrawl
policy-based governance
bitstream file
intellectual property security
intellectual properties
industrial property
FPGA security
FPGA designs
FPGA bitstream security
field programmable gate arrays
encryption
composability
Bitstream Protection
bitstream lifecycle

biblio

Kerberos: a 48-Channel Analog Processing Platform for Scalable Readout of Large SDD Arrays

Submitted by aekwall on Mon, 10/19/2020 - 10:59am

scalable readout
low-cost multichannel readout option
monolithic array
multichannel scalable analog processing
Neutrino sources
nuclear electronics
pixellated detectors
position sensitive particle detectors
Preamplifiers
readout electronics
scalable processing solution
KATRIN experiment
SDD arrays
semiconductor counters
simple cost multichannel readout option
solid scintillation detectors
spectroscopic quality
sterile neutrino existence
TRISTAN detector development
TRISTAN project
viable processing solution
Metrics
field programmable gate arrays
Cryptography
Resiliency
Human behavior
pubcrawl
data acquisition
Semiconductor device measurement
Kerberos
Physics
Detectors
16-channel integrated programmable analog pulse processors
48-channel analog processing platform
analog ASIC-based solution
application specific integrated circuits
back-end electronics
beta-decay spectroscopy
continuous spectrum
detection modules
digital pulse processor

biblio

Sampling Time Adaptive Single-Photon Compressive Imaging

Submitted by aekwall on Mon, 09/14/2020 - 11:30am

field-programmable gate array
time-adaptive sampling method
Time-adaptive sampling
threshold of light intensity estimation accuracy.
single photon compressive imaging
self-adapting adjustment
sampling-time-adaptive single-photon compressive imaging
sampling time
sampling methods
sampling control module
light intensity estimation accuracy
Imaging
image sampling
field programmable gate arrays
compressive sampling
Image reconstruction
Photonics
estimation
Image coding
privacy
composability
pubcrawl
Resiliency
cyber-physical systems
Time measurement

biblio

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Submitted by aekwall on Tue, 09/08/2020 - 9:12am

Internet key exchange protocol
IPsec
4-dimension chaotic system
chaotic cryptosystem
chaotic cryptosystem solution
data phase transfer
FPGA implementation
IKE
IKE protocol
securing communications
keys phase exchange
man in the middle attack
network communication domain
network protocol
SA
security association attack
word length 128 bit
computer network security
IPSec protocol
chaotic cryptography
chaotic communication
Predictive Metrics
DH-HEMTs
internet
Cryptography
Synchronization
composability
pubcrawl
Resiliency
Protocols
Cryptographic Protocols
FPGA
field programmable gate arrays

biblio

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

Submitted by aekwall on Tue, 09/08/2020 - 9:11am

chaotic communication
reconfigurable hardware
random number sequence
human body
Hopfield neural networks
Hopfield neural nets
encryption circuit
dynamic systems
chaotic synchronization
chaotic signal simulation
asymmetric cryptography method
reconfigurable architectures
chaotic cryptography
field programmable gate arrays
Predictive Metrics
Dynamical Systems
random number generation
Neural networks
Synchronization
synchronisation
composability
pubcrawl
Resiliency
information security
Cryptography
FPGA

biblio

Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA

Submitted by grigby1 on Fri, 09/04/2020 - 2:37pm

32/34/26-instance parallelization
brute force attacks
single Virtex-7 FPGA device
pre-image brute-force attack
pipeline processing
MD5 hash generation
MD5 hash algorithm
LUT
IP core
HDL
Hardware design languages
guess password generation
Cryptography
field programmable gate arrays
gpu
policy-based governance
Human Factors
password
pubcrawl
Generators
Hardware
computer architecture
Hardware Implementation

biblio

High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA

Submitted by grigby1 on Fri, 09/04/2020 - 2:36pm

Hardware
Xilinx XC3S1600E-4 FPGA device
stream cipher
RC4 algorithm
RC4
random-access storage
pubcrawl
process control
policy-based governance
on-chip BRAM
main controller
key searching unit
key searching speed
Human Factors
High Speed Parallel RC4 Key Searching Brute Force Attack
block RAM
frequency 128 MHz
FPGA
forecast keying methods
Force
field programmable gate arrays
field programmable gate array
encryption
Cryptography
Clocks
clock rate
Ciphers
brute force attacks
Brute force

biblio

SACHa: Self-Attestation of Configurable Hardware

Submitted by aekwall on Mon, 08/17/2020 - 10:36am

hardware-software system
tamper-resistant hardware module
Software
self-attestation
SACHa
Resiliency
remote attacks
Read only memory
pubcrawl
Protocols
physical attacks
Microprocessors
intended application code
Human behavior
attestation
hardware-based attestation
Hardware
FPGAs
Field-Programmable Gate Arrays
field programmable gate arrays
embedded systems
embedded software
embedded device
device attestation
configurable hardware
configurable FPGA hardware
computer architecture
composability

biblio

A New Pay-Per-Use Scheme for the Protection of FPGA IP

Submitted by grigby1 on Thu, 07/30/2020 - 12:53pm

complex FPGA designs
ip protection
reusable intellectual property design blocks
Physical Unclonable Function
pay-per-use
IP instance
IP infringement
FSM
FPGA IP vendor
FPGA IP protection
finite state machine
Field-Programmable Gate Arrays
Design methodology
copy protection
logic design
application specific integrated circuits
finite state machines
Licenses
composability
PUF
industrial property
field programmable gate arrays
Resiliency
resilience
policy-based governance
pubcrawl
IP networks
security

biblio

A hardware intellectual property protection scheme based digital compression coding technology

Submitted by grigby1 on Thu, 07/30/2020 - 12:50pm

Resiliency
intellectual property
intellectual property security
IP core watermark
IP networks
ip protection
policy-based governance
pubcrawl
resilience
industrial property
resource utilization
Robustness
security
surrounding circuit
Table lookup
watermark information
Watermarking
composability
image watermarking
hardware intellectual property protection
hardware circuit
Hardware
FPGA circuit
FPGA
field programmable gate arrays
encoding
embedding cost
Digital Watermark
digital compression coding technology
decoding function
data compression
Cryptography
Compression coding

« first
‹ previous
1
2
3
4
5
6
7
8
9
…
next ›
last »

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

field programmable gate arrays

FPGA Bitstream Security: A Day in the Life

Kerberos: a 48-Channel Analog Processing Platform for Scalable Readout of Large SDD Arrays

Sampling Time Adaptive Single-Photon Compressive Imaging

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA

High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA

SACHa: Self-Attestation of Configurable Hardware

A New Pay-Per-Use Scheme for the Protection of FPGA IP

A hardware intellectual property protection scheme based digital compression coding technology