FPGA

biblio

High Performance Data Encryption with AES Implementation on FPGA

Submitted by grigby1 on Tue, 12/01/2020 - 12:46pm

FPGA
Resiliency
resilience
Random access memory
pubcrawl
Pipelines
low latency
intrusion detection system
IDS
high speed
high performance data encryption
AES
field programmable gate arrays
encryption speed
encryption
Data Security
Cryptography
composability
BIGDATA
Big Data
AES implementation
AES encryption algorithm

biblio

FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

Submitted by aekwall on Mon, 11/09/2020 - 12:31pm

logic design
ring oscillator physical unclonable function
ring oscillator based physical unclonable function
Ring Oscillator
Resiliency
PUF
pubcrawl
policy-based governance
Oscillators
logic obfuscation
Logic gates
composability
IP piracy
IP obfuscation
hardware obfuscation
FPGA IP obfuscation
FPGA based IP protection scheme
FPGA based designs
FPGA
field programmable gate arrays
Cryptography

biblio

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Submitted by aekwall on Tue, 09/08/2020 - 9:12am

Internet key exchange protocol
IPsec
4-dimension chaotic system
chaotic cryptosystem
chaotic cryptosystem solution
data phase transfer
FPGA implementation
IKE
IKE protocol
securing communications
keys phase exchange
man in the middle attack
network communication domain
network protocol
SA
security association attack
word length 128 bit
computer network security
IPSec protocol
chaotic cryptography
chaotic communication
Predictive Metrics
DH-HEMTs
internet
Cryptography
Synchronization
composability
pubcrawl
Resiliency
Protocols
Cryptographic Protocols
FPGA
field programmable gate arrays

biblio

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

Submitted by aekwall on Tue, 09/08/2020 - 9:11am

chaotic communication
reconfigurable hardware
random number sequence
human body
Hopfield neural networks
Hopfield neural nets
encryption circuit
dynamic systems
chaotic synchronization
chaotic signal simulation
asymmetric cryptography method
reconfigurable architectures
chaotic cryptography
field programmable gate arrays
Predictive Metrics
Dynamical Systems
random number generation
Neural networks
Synchronization
synchronisation
composability
pubcrawl
Resiliency
information security
Cryptography
FPGA

biblio

High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA

Submitted by grigby1 on Fri, 09/04/2020 - 2:36pm

Hardware
Xilinx XC3S1600E-4 FPGA device
stream cipher
RC4 algorithm
RC4
random-access storage
pubcrawl
process control
policy-based governance
on-chip BRAM
main controller
key searching unit
key searching speed
Human Factors
High Speed Parallel RC4 Key Searching Brute Force Attack
block RAM
frequency 128 MHz
FPGA
forecast keying methods
Force
field programmable gate arrays
field programmable gate array
encryption
Cryptography
Clocks
clock rate
Ciphers
brute force attacks
Brute force

biblio

A hardware intellectual property protection scheme based digital compression coding technology

Submitted by grigby1 on Thu, 07/30/2020 - 12:50pm

Resiliency
intellectual property
intellectual property security
IP core watermark
IP networks
ip protection
policy-based governance
pubcrawl
resilience
industrial property
resource utilization
Robustness
security
surrounding circuit
Table lookup
watermark information
Watermarking
composability
image watermarking
hardware intellectual property protection
hardware circuit
Hardware
FPGA circuit
FPGA
field programmable gate arrays
encoding
embedding cost
Digital Watermark
digital compression coding technology
decoding function
data compression
Cryptography
Compression coding

biblio

DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture

Submitted by aekwall on Mon, 06/29/2020 - 11:57am

deeply programmable packet-switching node
SDN
Firewalls (computing)
DoS
Software-Defined Networks
5G
data plane
denial-of-service attack
denial-of-service attacks
architectural model
deep network programmability
software-defined networking
DoS attack mitigation
DoS attack redirection
DoS attacks mitigation
DoS traffic
DPN
packet switching
packet-switching nodes
switches price
DDoS attack mitigation
computer network management
DDoS
field programmable gate arrays
FPGA
firewall
telecommunication traffic
authorisation
Hardware
Software
computer architecture
computer network security
SDN network
software defined networking
Resiliency
Human behavior
pubcrawl
composability
Metrics
internet
Filtering

biblio

Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs

Submitted by grigby1 on Fri, 06/12/2020 - 11:09am

high-quality hash functions
Resiliency
resilience
Registers
reconfigurable hash function
reconfigurable design
reconfigurable architectures
pubcrawl
network flow hashing
multiobjective linear genetic programming
Monitoring
Linear programming
IP networks
Compositionality
high speed computer networks
hash function design
hash algorithms
hardware acceleration
Hardware
genetic programming
genetic algorithms
FPGA
field programmable gate arrays
field programmable gate array
fast reconfigurable hash functions
Cryptography

biblio

A Nearest Neighbor Search Engine Using Distance-Based Hashing

Submitted by grigby1 on Fri, 05/22/2020 - 1:38pm

query processing
query point
high-dimensional data
hardware search engine
FPGA-based nearest neighbor search engine
flexible distance-based hashing
distance based hashing
nearest neighbor search algorithm
nearest neighbor search
file organisation
pubcrawl
search problems
search engines
nearest neighbour methods
Measurement
Metrics
parallel processing
field programmable gate arrays
FPGA

biblio

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF

Submitted by grigby1 on Fri, 04/24/2020 - 11:02am

PUF
Monte Carlo analysis
Monte Carlo methods
oscillating behaviors
oscillating systems
Oscillators
physical unclonable functions
privacy
pubcrawl
Modeling Attacks
PUF architecture
resilience
Resiliency
Resistance
security
security of data
Unclonability
arbiter PUF
Metrics
Measurement
Mathematical model
learning (artificial intelligence)
Integrated circuit modeling
FPGA
field programmable gate arrays
Cryptography
conventional machine learning
composability
Chua's oscillator circuit
Chua's Oscillator
chaotic oscillator
chaotic behaviour
chaos

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Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

FPGA

High Performance Data Encryption with AES Implementation on FPGA

FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

FPGA Implementation of Internet Key Exchange Based on Chaotic Cryptosystem

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body

High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA

A hardware intellectual property protection scheme based digital compression coding technology

DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture

Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs

A Nearest Neighbor Search Engine Using Distance-Based Hashing

Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF