Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
FPGA
biblio
A high speed implementation counter mode cryptography using hardware parallelism
Submitted by grigby1 on Thu, 04/20/2017 - 11:41am
parallel computing
hardware parallelism
Heracles toolkit
high speed implementation counter mode cryptography
network-on-chip
network on chip
Network on Chip(NoC)
network on chip security
NoC
graphics processing units
pubcrawl
Resiliency
Scalability
secure data transmission
security mechanisms
Software algorithms
unsecured networks
DES
Big Data
composability
Counter Mode Cryptography (CTR)
CPU
Cryptography
CTR
data encryption standard core
Data Encryption Standard (DES)
Algorithm design and analysis
encryption
field programmable gate arrays
FPGA
FPGA board
gpu
Grafic Process Unite(GPU)
graphics processing unit
biblio
Towards an FPGA-based network layer filter for the Internet of Things edge devices
Submitted by grigby1 on Thu, 04/20/2017 - 11:40am
IPv6
system-on-chip implementation
system-on-chip
security
Scalability
Resiliency
pubcrawl
personal area networks
Packet Filter
network on chip security
network on chip
low-power resource constrained devices
IPv6 Link-local address calculator
6LoWPAN
Internet-of-Things (IoT)
Internet of Things edge devices
Internet of Things
IEEE 802.15.4 radio modules
FPGA-based network layer filter
FPGA
Filters
field programmable gate arrays
Contiki-OS
composability
6LoWPAN adaptation layer
biblio
Bypassing Parity Protected Cryptography Using Laser Fault Injection in Cyber-Physical System
Submitted by grigby1 on Mon, 03/20/2017 - 9:45am
injection
Resiliency
register bit-flip
pubcrawl
parity
Metrics
Lightweight Ciphers
laser fault injection
injection attacks
command injection attacks
FPGA
cyber-physical system
controller area network security
concurrent error detection (CED)
concurrency security
concurrency and security
composability
biblio
An efficient hardware implementation of few lightweight block cipher
Submitted by grigby1 on Wed, 03/08/2017 - 1:33pm
FPGA
sensor node
security system
Schedules
RFID
resource-efficient cryptographic incipient
radiofrequency identification
radio-frequency identification
pubcrawl170112
high level synthesis
Hardware Implementation
Hardware
Algorithm design and analysis
field programmable gate arrays
Field Programmable Gate Array (FPGA)
FeW lightweight block cipher
FeW cryptography algorithm
FeW Algorithm
Feistel structure
encryption
Cryptography
Ciphers
Block Cipher
biblio
"Application specific processor design for DCT based applications"
Submitted by grigby1 on Tue, 02/14/2017 - 12:10pm
FPGA
Watermarking
Transform coding
pubcrawl170102
parallel architectures
parallel architecture
one dimensional DCT
MicroBlaze softcore processer
JPEG compression
image watermarking
image encryption
IDCT hardware
Hardware
Application Specific Processor
field programmable gate arrays
field programmable gate array
Europe
discrete cosine transforms
discrete cosine transform
DCT based image watermarking
DCT based applications
Channel estimation
ASP
Application specific processors
application specific processor design
biblio
Multi-objective Module Partitioning Design for Dynamic and Partial Reconfigurable System-on-chip Using Genetic Algorithm
Submitted by BrandonB on Wed, 05/06/2015 - 1:31pm
Dynamic and partial reconfiguration
FPGA
genetic algorithm
Module partitioning solution
Multi-objective problem
SoC
biblio
An FPGA implementation of high-throughput key-value store using Bloom filter
Submitted by BrandonB on Wed, 05/06/2015 - 10:52am
arrays
Bloom filter
cuckoo hashing algorithm
data structures
field programmable gate arrays
file organisation
FPGA
FPGA implementation
Hardware
hash tables
high-throughput key-value store
Information filters
Key-value Store
Random access memory
Software
biblio
EM-based detection of hardware trojans on FPGAs
Submitted by BrandonB on Wed, 05/06/2015 - 10:37am
Layout
Xilinx Virtex-II Pro target
Trojan placement
Trojan horses
Software
side-channel analysis
sequential denial-of-service
RapidSmith
Probes
malicious circuitry
logic design
AES design
invasive software
Hardware Trojan injection
hardware Trojan detection
Hardware
FPGA
field programmable gate arrays
EM-based detection
EM measurement
electromagnetic emanation
Clocks
biblio
LUT based secure cloud computing #x2014; An implementation using FPGAs
Submitted by BrandonB on Tue, 05/05/2015 - 8:24am
Games
Table lookup
suitable hardware platform
security requirements
security of data
secure cloud computing scheme
program security
pattern clustering
LUT based secure cloud computing
look-up table
k-means clustering algorithm
Big Data
FPGA
Formalization
field programmable gate arrays
encryption
data sharing
data security problem
cryptographic techniques
Cloud Computing
big data processing
biblio
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking
Submitted by BrandonB on Fri, 05/01/2015 - 8:10am
Pipelines
Trusted Computing
stack smashing
Software
security of data
security
Runtime Security
runtime attacks
Runtime
reconfigurable dynamic trusted platform module
Reconfigurable Architecture
processor pipeline
Benchmark testing
Instruction Set Architecture
FPGA
formal verification
field programmable gate arrays
dynamic TPM design
Dynamic TPM
control flow checking
computer architecture
code reuse
buffer overflow
« first
‹ previous
1
2
3
4
5
6
7
8
9
