Intellectual Property Protection 2015

	Intellectual Property Protection 2015

Intellectual Property protection continues to be a matter of major research interest.  The articles cited here look at hardware security, provenance and piracy prevention.  The topic is related to the Science of Security regarding resilience, policy-based governance, and composability.  Articles cited were presented in 2015.

Rajendran, J.; Huan Zhang; Chi Zhang; Rose, G.S.; Youngok Pino; Sinanoglu, O.; Karri, R., "Fault Analysis-Based Logic Encryption," in Computers, IEEE Transactions on, vol. 64, no. 2, pp. 410-424, Feb. 2015. doi: 10.1109/TC.2013.193

Abstract: Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

Keywords: cryptography; fault diagnosis; integrated circuit design; integrated circuit testing; invasive software; logic gates; Hamming distance; IC design industry; IC testing; fault analysis-based logic encryption; fault propagation analysis; gates; hardware Trojans; integrated circuit design industry; random logic encryption; supply chain attacks; Circuit faults; Encryption; Foundries; Integrated circuits; Logic gates; Testing; Automatic test pattern generation; IC piracy; IP piracy; combinational logic circuit; hardware security; integrated circuit testing; logic obfuscation (ID#: 15-8674)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6616532&isnumber=7006872

Yasin, M.; Rajendran, J.; Sinanoglu, O.; Karri, R., "On Improving the Security of Logic Locking," in Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1-1, 22 December 2015. doi: 10.1109/TCAD.2015.2511144

Abstract: Due to globalization of Integrated Circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware trojans. EPIC [1] locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output. We then develop techniques to fix this vulnerability and make an attacker’s effort truly exponential in the number of inserted keys. We introduce a new security metric and a method to deliver strong logic locking.

Keywords: Foundries; Hardware; Integrated circuits; Logic gates; Reverse engineering; Trojan horses; Design for trust; Hardware security; IP piracy; IP protection; Logic encryption (ID#: 15-8675)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7362173&isnumber=6917053

Yu-Wei Lee; Touba, N.A., "Improving Logic Obfuscation via Logic Cone Analysis," in Test Symposium (LATS), 2015 16th Latin-American, pp.1-6, 25-27 March 2015. doi: 10.1109/LATW.2015.7102410

Abstract: Logic obfuscation can protect designs from reverse engineering and IP piracy. In this paper, a new attack strategy based on applying brute force iteratively to each logic cone is described and shown to significantly reduce the number of brute force key combinations that need to be tried by an attacker. It is shown that inserting key gates based on MUXes is an effective approach to increase security against this type of attack. Experimental results are presented quantifying the threat posed by this type of attack along with the relative effectiveness of MUX key gates in countering it.

Keywords: logic design; logic gates; IP piracy; MUX key gates; attacker; brute force key combinations; logic cone analysis; logic obfuscation; reverse engineering; Force; IP networks; Integrated circuits; Interference; Logic gates; Reverse engineering; Security (ID#: 15-8676)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7102410&isnumber=7102396

Kan Xiao; Forte, D.; Tehranipoor, M.M., "Efficient and Secure Split Manufacturing via Obfuscated Built-in Self-Authentication," in Hardware Oriented Security and Trust (HOST), 2015 IEEE International Symposium on, pp. 14-19, 5-7 May 2015. doi: 10.1109/HST.2015.7140229

Abstract: The threats of reverse-engineering, IP piracy, and hardware Trojan insertion in the semiconductor supply chain are greater today than ever before. Split manufacturing has emerged as a viable approach to protect integrated circuits (ICs) fabricated in untrusted foundries, but has high cost and/or high performance overhead. Furthermore, split manufacturing cannot fully prevent untargeted hardware Trojan insertions. In this paper, we propose to insert additional functional circuitry called obfuscated built-in self-authentication (OBISA) in the chip layout with split manufacturing process, in order to prevent reverse-engineering and further prevent hardware Trojan insertion. Self-tests are performed to authenticate the trustworthiness of the OBISA circuitry. The OBISA circuit is connected to original design in order to increase the strength of obfuscation, thereby allowing a higher layer split and lower overall cost. Additional fan-outs are created in OBISA circuitry to improve obfuscation without losing testability. Our proposed gating mechanism and net selection method can ensure negligible overhead in terms of area, timing, and dynamic power. Experimental results demonstrate the effectiveness of the proposed technique in several benchmark circuits.

Keywords: foundries; integrated circuit manufacture; integrated circuit reliability; invasive software; reverse engineering; supply chains; IP piracy; OBISA circuit; chip layout; hardware Trojan insertion; integrated circuits; obfuscated built-in self-authentication; reverse engineering; semiconductor supply chain; split manufacturing; trustworthiness; untrusted foundries; Delays; Fabrication; Foundries; Layout; Logic gates (ID#: 15-8677)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7140229&isnumber=7140225

sin, M.; Mazumdar, B.; Ali, S.S.; Sinanoglu, O., "Security Analysis of Logic Encryption Against the Most Effective Side-Channel Attack: DPA," in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on, pp. 97-102, 12-14 Oct. 2015. doi: 10.1109/DFT.2015.7315143

Abstract: Logic encryption has recently gained interest as a countermeasure against IP piracy and reverse engineering attacks. A secret key is used to lock/encrypt an IC such that the IC will not be functional without being activated with the correct key. Existing attacks against logic encryption are of theoretical and/or algorithmic nature. In this paper, we evaluate for the first time the security of logic encryption against side-channel attacks. We present a differential power analysis attack against random and strong logic encryption techniques. The proposed attack is highly effective against random logic encryption, revealing more than 70% of the key bits correctly in 50% of the circuits. However, in the case of strong logic encryption, which exhibits an inherent DPA-resistance, the attack could reveal more than 50% of the key bits in only 25% of the circuits.

Keywords: integrated logic circuits; private key cryptography; DPA-resistance; IC encryption; IC lock; IP piracy; differential power analysis attack; key bits; logic encryption security analysis; random-logic encryption technique; reverse engineering attacks; secret key; side-channel attack; strong logic encryption technique; Algorithm design and analysis; Benchmark testing; Encryption; IP networks; Integrated circuits; Reverse engineering (ID#: 15-8678)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7315143&isnumber=7315124

Dunbar, C.; Gang Qu, "A Practical Circuit Fingerprinting Method Utilizing Observability Don't Care Conditions," in Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE, pp. 1-6, 8-12 June 2015. doi: 10.1145/2744769.2744780

Abstract: Circuit fingerprinting is a method that adds unique features into each copy of a circuit such that they can be identified for the purpose of tracing intellectual property (IP) piracy. It is challenging to develop effective fingerprinting techniques because each copy of the IP must be made different, which increases the design and manufacturing cost. In this paper, we explore the Observability Don't Care (ODC) conditions to create multiple fingerprinting copies of a design IP (e.g. in the form of gate level layout) with minute changes. More specifically, we find locations in the given circuit layout where we can replace a gate with another gate and some wires without changing the functionality of the circuit. However, as expected, this could introduce design overhead. Our experimental results show that, although we can embed fingerprints of up to 1438 bits, there is an average of 10.9% area increase, 50.5% delay increase, and 9.4% power increase on circuits in the MCNC and ISCAS 85 benchmark suites. We further propose a fingerprinting heuristics under delay constraints to help us reduce area and power overhead.

Keywords: circuit layout; embedded systems; industrial property; system-on-chip; IP; ISCAS 85 benchmark; circuit fingerprinting; circuit layout; fingerprinting copies; fingerprinting techniques; intellectual property piracy; Fingerprint recognition; Integrated circuits; Inverters; Layout; Logic gates (ID#: 15-8679)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7167298&isnumber=7167177

Mishra, P.; Bhunia, S.; Ravi, S., "Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems," in VLSI Design (VLSID), 2015 28th International Conference on, pp. 3-5, 3-7 Jan. 2015. doi: 10.1109/VLSID.2015.110

Abstract: Summary form only given. Reusable hardware intellectual property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting aggressive time-to-market constraints. However, growing reliance on reusable pre-verified hardware IPs and wide array of CAD tools during SoC design - often gathered from untrusted 3rd party vendors - severely affects the security and trustworthiness of SoC computing platforms. Major security issues in the hardware IPs at different stages of SoC life cycle include piracy during IP evaluation, reverse engineering, cloning, counterfeiting, as well as malicious hardware modifications. The global electronic piracy market is growing rapidly and is now estimated to be $1B/day, of which a significant part is related to hardware IPs. Furthermore, use of untrusted foundry in a fabless business model greatly aggravates the SoC security threats by introducing vulnerability of malicious modifications or piracy during SoC fabrication. Due to ever-growing computing demands, modern SoCs tend to include many heterogeneous processing cores, scalable communication network, together with reconfigurable cores e.g. embedded FPGA in order to incorporate logic that is likely to change as standards and requirements evolve. Such design practices greatly increase the number of untrusted components in the SoC design flow and make the overall system security a pressing concern. There is a critical need to analyze the SoC security issues and attack models due to involvement of multiple untrusted entities in SoC design cycle - IP vendors, CAD tool developers, and foundries - and develop low-cost effective countermeasures. These countermeasures would encompass encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspects of SoC to enable trusted operation with untrusted components. In this tutorial, we plan to prov- de a comprehensive coverage of both fundamental concepts and recent advances in validation of security and trust of hardware IPs. The tutorial also covers the security and debug trade-offs in modern SoCs e.g., more observability is beneficial for debug whereas limited observability is better for security. It examines the state-of-the-art in research in this challenging area as well as industrial practice, and points to important gaps that need to be filled in order to develop a validation and debug flow for secure SoC systems. The tutorial presenters (one industry expert and two faculty members) will be able to provide unique perspectives on both academic research and industrial practices. The selection of topics covers a broad spectrum and will be of interest to a wide audience including design, validation, security, and debug engineers. The proposed tutorial consists of five parts. The first part introduces security vulnerabilities and various challenges associated with trust validation for hardware IPs. Part II covers various security attacks and countermeasures. Part III covers both formal methods and simulation-based approaches for security and trust validation. Part IV presents the conflicting requirements between security and debug during SoC development and ways to address them. Part V covers real-life examples of security failures and successful countermeasures in industry. Finally, Part VI concludes this tutorial with discussion on emerging issues and future directions.

Keywords: computer debugging; embedded systems; industrial property; security of data; system-on-chip; SoC computing platforms; debug flow; embedded systems; formal methods; hardware IP; reusable hardware intellectual property; security attacks; security failures; security validation; security vulnerabilities; system-on-chip; trust validation; Awards activities; Design automation; Hardware; Security; System-on-chip; Tutorials; Very large scale integration (ID#: 15-8680)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7031691&isnumber=7031671

Zhang, J., "A Practical Logic Obfuscation Technique for Hardware Security," in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP, no. 99, pp.1-1, June 2015. doi: 10.1109/TVLSI.2015.2437996

Abstract: A number of studies of hardware security aim to thwart piracy, overbuilding, and reverse engineering (RE) by obfuscating and/or camouflaging. However, these techniques incur high overheads, and integrated circuit (IC) camouflaging cannot provide any protection for the gate-level netlist of the third party intellectual property (IP) core or the single large monolithic IC. In order to circumvent these weaknesses, this brief elaborately analyzes these hardware security techniques and proposes a practical logic obfuscation method with low overheads to prevent an adversary from RE both the gate-level netlist and the layout-level geometry of IP/IC and protect IP/IC from piracy and overbuilding. Experimental evaluations demonstrate the low area, power, and zero performance overhead of the proposed obfuscation technique.

Keywords: Benchmark testing; Hardware; Integrated circuits; Inverters; Licenses; Logic gates; Security; Hardware security; intellectual property (IP) protection; logic obfuscation; overbuilding; physical unclonable function (PUF); piracy; reverse engineering (RE) (ID#: 15-8681)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7128395&isnumber=4359553

Chari, K.S.; Sharma, M., "Performance of IC Layout Design Diagnostic Tool," in Communication Technologies (GCCT), 2015 Global Conference on, pp. 332-337, 23-24 April 2015. doi: 10.1109/GCCT.2015.7342678

Abstract: The staggering evolution of electronic products in all spheres of human life has been possible because of the advancements in the Integrated Circuit (IC) design and technologies. The complexities of the ICs have grown tremendously over the years, so does the intellectual capital of resources and man years of efforts in their creations. With increasing emphasis on protection of ICs, the issues of Intellectual Property Rights (IPR) pertaining to IC layout, the backbone of implemented functionality, have become crucial. The matters of IPR also touch on several legal and ethical issues associated with the layout creations. In this context, analyzing the distinctness in IC Layout Design (LD) and knowing the unique and common parts in different IC LDs of concern has become important both from IP protection aspects as well as design perspective of tagging the layouts for their content. A robust analytical evaluation of designs could immensely help in catching piracy of IC Designs in addition to assisting the screening processes followed before granting IPR to claimants. Authors have previously presented some results on custom designed IC Layout Design Diagnostic Tool (ICLDDT) for this purpose. In the present paper, the abilities of a more advanced version, Version 2 of this tool is investigated further and results of performance reported.

Keywords: industrial property; integrated circuit layout; IC layout design diagnostic tool; IP protection; IPR; catching piracy; electronic products; human life; intellectual property rights; robust analytical evaluation; screening process; staggering evolution; Complexity theory; Geometry; Integrated circuit layout; Intellectual property; Layout; Shape; ICLDDT; IPR; Integrated Circuit Layout Design(ICLD); Layout and geometry comparison; geometry equivalence check (ID#: 15-8682)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7342678&isnumber=7342608

Plaza, S.M.; Markov, I.L., "Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking," in Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 34, no. 6, pp. 961-971, June 2015. doi: 10.1109/TCAD.2015.2404876

Abstract: The increasing IC manufacturing cost encourages a business model where design houses outsource IC fabrication to remote foundries. Despite cost savings, this model exposes design houses to IC piracy as remote foundries can manufacture in excess to sell on the black market. Recent efforts in digital hardware security aim to thwart piracy by using XOR-based chip locking, cryptography, and active metering. To counter direct attacks and lower the exposure of unlocked circuits to the foundry, we introduce a multiplexor-based locking strategy that preserves test response allowing IC testing by an untrusted party before activation. We demonstrate a simple yet effective attack against a locked circuit that does not preserve test response, and validate the effectiveness of our locking strategy on IWLS 2005 benchmarks.

Keywords: integrated circuit manufacture; integrated circuit modelling; logic design; logic testing; IC manufacturing cost; IC piracy; IWLS 2005 benchmarks; XOR-based chip locking; active metering; business model; cost savings; counter direct attacks; cryptography; design houses outsource IC fabrication; digital hardware security; remote foundries; test-aware logic locking; third-shift problem; thwart piracy; Cryptography; Fabrication; Integrated circuit modeling; Logic gates; Tin; Vectors; Chip locking; EPIC; IP protection; chip locking; design for testability; ending piracy of integrated circuits (EPIC); secure hardware; third-shift problem (ID#: 15-8683)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7045595&isnumber=7110649

Bossuet, L.; Fischer, V.; Bayon, P., "Contactless Transmission of Intellectual Property Data to Protect FPGA Designs," in Very Large Scale Integration (VLSI-SoC), 2015 IFIP/IEEE International Conference on, pp. 19-24, 5-7 Oct. 2015. doi: 10.1109/VLSI-SoC.2015.7314385

Abstract: Over the past 10 years, the designers of intellectual properties (IP) have faced increasing threats including illegal copy or cloning, counterfeiting, reverse-engineering. This is now a critical issue for the microelectronics industry, mainly for fabless designers and FPGA designers. The design of a secure, efficient, lightweight protection scheme for design data is a serious challenge for the hardware security community. In this context, this paper presents the first ultra-lightweight transmitter using side channel leakage based on electromagnetic emanation to send embedded IP identity discreetly and quickly. In addition, we present our electromagnetic test bench and a coherent demodulation method using slippery window spectral analysis to recover data outside the device. The hardware resources occupied by the transmitter represent less than 0.022% of a 130 nm Microsemi Fusion FPGA. Experimental results show that the demodulation method success to provide IP data with a bit rate equal to 500 Kbps.

Keywords: copy protection; field programmable gate arrays; industrial property; logic design; radio transmitters; FPGA design protection; Microsemi Fusion FPGA; bit rate 500 kbit/s; contactless transmission; electromagnetic emanation; embedded IP identity; fabless design; intellectual property data; microelectronics industry; side channel leakage; ultralightweight transmitter; Bit rate; Demodulation; Electromagnetics; Field programmable gate arrays; Hardware; Spectral analysis; Transmitters; IP protection; electromagnetic emanation analysis; side channel (ID#: 15-8684)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7314385&isnumber=7314373

Colombier, B.; Bossuet, L.; Hely, D., "Reversible Denial-of-Service by Locking Gates Insertion for IP Cores Design Protection," in VLSI (ISVLSI), 2015 IEEE Computer Society Annual Symposium on, pp. 210-215, 8-10 July 2015. doi: 10.1109/ISVLSI.2015.54

Abstract: Nowadays, electronics systems design is a complex process. A design-and-reuse model has been adopted, and the vast majority of designers integrate third party intellectual property (IP) cores in their design in order to reduce time to market. Due to their immaterial form and high market value, IP cores are exposed to threats such as cloning and illegal copying. In order to fight these threats, we propose to achieve functional locking, equivalent to a trigger able and reversible denial-of-service. This is done by inserting locking gates at specific locations in the net list, allowing to force outputs at a fixed value. We developed a new method based on graph exploration techniques for locking gates insertion. It selects candidate nodes ten thousand times faster than state-of-the-art fault analysis-based logic masking techniques. Methods are then compared on ISCAS'85 combinational benchmarks.

Keywords: copy protection; copyright; graph theory; logic circuits; logic design; microprocessor chips; IP cores design protection; cloning threats; design-and-reuse model; electronics systems design; fault analysis-based logic masking techniques; functional locking; graph exploration techniques; illegal copying; locking gates insertion; reversible denial-of-service; third party intellectual property; Algorithm design and analysis; Benchmark testing; Circuit faults; Correlation; Force; Logic gates; Security; Intellectual property protection; functional locking; graph analysis; logic masking (ID#: 15-8685)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7309567&isnumber=7308659

Yao, Song; Chen, Xiaoming; Zhang, Jie; Liu, Qiaoyi; Wang, Jia; Xu, Qiang; Wang, Yu; Yang, Huazhong, "FASTrust: Feature Analysis for Third-party IP Trust Verification," in Test Conference (ITC), 2015 IEEE International, pp. 1-10, 6-8 Oct. 2015. doi: 10.1109/TEST.2015.7342417

Abstract: Third-party intellectual property (3PIP) cores are widely used in integrated circuit designs. It is essential and important to ensure their trustworthiness. Existing hardware trust verification techniques suffer from high computational complexity, low extensibility, and inability to detect implicitly-triggered hardware trojans (HTs). To tackle the above problems, in this paper, we present a novel 3PIP trust verification framework, named FASTrust, which conducts HT feature analysis on the flip-flop level control-data flow graph (CDFG) of the circuit. FASTrust is not only able to identify existing explicitly-triggered and implicitly-triggered HTs appeared in the literature in an efficient and effective manner, but more importantly, it also has the unique advantage of being scalable to defend against future and more stealthy HTs by adding new features to the system.

Keywords: Combinational circuits; Feature extraction; Hardware; Integrated circuit modeling; Trojan horses; Wires; Hardware Trojan; feature analysis; hardware security; third-party intellectual property (ID#: 15-8686)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7342417&isnumber=7342364

Machado, R.C.S.; Boccardo, D.R.; Pereira De Sa, V.G.; Szwarcfiter, J.L., "Fair Fingerprinting Protocol for Attesting Software Misuses," in Availability, Reliability and Security (ARES), 2015 10th International Conference on, pp. 110-119, 24-27 Aug. 2015. doi: 10.1109/ARES.2015.29

Abstract: Digital watermarks embed information into a host artifact in such a way that the functionalities of the artifact remain unchanged. Allowing for the timely retrieval of authorship/ownership information, and ideally hard to be removed, watermarks discourage piracy and have thus been regarded as important tools to protect the intellectual property. A watermark aimed at uniquely identifying an artifact is referred to as a fingerprint. After presenting a formal definition of digital watermarks, we introduce an unbiased fingerprinting protocol -- based on oblivious transfer -- that lends no advantage to the prosecuting party in a dispute around intellectual property breach.

Keywords: computer crime; industrial property; software engineering; watermarking; authorship-ownership information; digital watermarks; fair fingerprinting protocol; intellectual property breach; oblivious transfer; piracy; prosecuting party; software misuses; unbiased fingerprinting protocol; Intellectual property; Protocols; Public key; Semantics; Software; Watermarking; oblivious transfer; software fingerprinting (ID#: 15-8687)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7299904&isnumber=7299862

Elmrabit, N.; Shuang-Hua Yang; Lili Yang, "Insider Threats in Information Security Categories and Approaches," in Automation and Computing (ICAC), 2015 21st International Conference on, pp. 1-6, 11-12 Sept. 2015. doi: 10.1109/IConAC.2015.7313979

Abstract: The main concern of most security experts in the last years is the need to mitigate insider threats. However, leaking and selling data these days is easier than before; with the use of the invisible web, insiders can leak confidential data while remaining anonymous. In this paper, we give an overview of the various basic characteristics of insider threats. We also consider current approaches and controls to mitigating the level of such threats by broadly classifying them into two categories.

Keywords: Internet; data privacy; security of data; confidential data; information security ;insider threats; invisible Web; security experts; Authorization; Cloud computing; Companies; Databases; Information security; Intellectual property; Insider threats; data leaking; insider attacks; insider predictions; privileged user abuse (ID#: 15-8688)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7313979&isnumber=7313638

Bidmeshki, M.-M.; Makris, Y., "Toward Automatic Proof Generation for Information Flow Policies in Third-Party Hardware IP," in Hardware Oriented Security and Trust (HOST), 2015 IEEE International Symposium on, pp. 163-168, 5-7 May 2015. doi: 10.1109/HST.2015.7140256

Abstract: The proof carrying hardware intellectual property (PCHIP) framework ensures trustworthiness by developing proofs for security properties designed to prevent introduction of malicious behaviors via third-party hardware IP. However, converting a design to a formal representation and developing proofs for the desired security properties is a cumbersome task for IP developers and requires extra knowledge of formal reasoning methods, proof development and proof checking. While security properties are generally specific to each design, information flow policies are a set of policies which ensure that no secret information is leaked through untrusted channels, and are mainly applicable to the designs which manipulate secret and sensitive data. In this work, we introduce the VeriCoq-IFT framework which aims to (i) automate the process of converting designs from HDL to the Coq formal language, (ii) generate security property theorems ensuring information flow policies, (iii) construct proofs for such theorems, and (iv) check their validity for the design, with minimal user intervention. We take advantage of Coq proof automation facilities in proving the generated theorems for enforcing these policies and we demonstrate the applicability of our automated framework on two DES encryption circuits. By providing essential information, the trustworthiness of these circuits in terms of information flow policies is verified automatically. Any alteration of the circuit description against information flow policies causes proofs to fail. Our methodology is the first but essential step in the adoption of PCHIP as a valuable method to authenticate the trustworthiness of third party hardware IP with minimal extra effort.

Keywords: formal languages; industrial property; theorem proving; trusted computing; Coq formal language; DES encryption circuits; HDL; PCHIP framework; VeriCoq-IFT framework; automatic proof generation; formal reasoning methods; information flow policies; malicious behaviors; proof carrying hardware intellectual property framework; proof checking; proof development; third-party hardware; Hardware; Hardware design languages; IP networks; Sensitivity; Trojan horses; Wires (ID#: 15-8689)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7140256&isnumber=7140225

Rass, Stefan; Schartner, Peter, "Licensed Processing of Encrypted Information," in Communications and Network Security (CNS), 2015 IEEE Conference on, pp. 703-704, 28-30 Sept. 2015. doi: 10.1109/CNS.2015.7346894

Abstract: We report on work in progress concerning a computational model for data processing in privacy. As a core design goal here, we will focus on how the data owner can authorize another party to process data on his behalf. In that scenario, the algorithm or software for the processing can even be provided by a third party. The goal is here to protect the intellectual property rights of all relevant players, while retaining an efficient system that allows data processing in distrusted environments, such as clouds.

Keywords: Cloud computing; Data processing; Encoding; Encryption; Licenses; cloud computing; cryptography; licensing; private function evaluation; security (ID#: 15-8690)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7346894&isnumber=7346791

Djouadi, S.M.; Melin, A.M.; Ferragut, E.M.; Laska, J.A.; Jin Dong; Drira, A., "Finite Energy and Bounded Actuator Attacks on Cyber-Physical Systems," in Control Conference (ECC), 2015 European, pp. 3659-3664, 15-17 July 2015. doi: 10.1109/ECC.2015.7331099

Abstract: As control system networks are being connected to enterprise level networks for remote monitoring, operation, and system-wide performance optimization, these same connections are providing vulnerabilities that can be exploited by malicious actors for attack, financial gain, and theft of intellectual property. Much effort in cyber-physical system (CPS) protection has focused on protecting the borders of the system through traditional information security techniques. Less effort has been applied to the protection of cyber-physical systems from intelligent attacks launched after an attacker has defeated the information security protections to gain access to the control system. In this paper, attacks on actuator signals are analyzed from a system theoretic context. The threat surface is classified into finite energy and bounded attacks. These two broad classes encompass a large range of potential attacks. The effect of theses attacks on a linear quadratic (LQ) control are analyzed, and the optimal actuator attacks for both finite and infinite horizon LQ control are derived, therefore the worst case attack signals are obtained. The closed-loop system under the optimal attack signals is given and a numerical example illustrating the effect of an optimal bounded attack is provided.

Keywords: actuators; closed loop systems; infinite horizon; linear quadratic control; networked control systems; security of data; signal processing; CPS protection; actuator signals; bounded actuator attacks; closed-loop system; control system networks; cyber-physical system protection; enterprise level networks; finite energy actuator attacks; infinite horizon LQ control; information security protections; information security techniques; intelligent attacks; linear quadratic control; optimal actuator attacks; optimal attack signals; remote monitoring; system theoretic context; system-wide performance optimization; Actuators; Closed loop systems; Computer science; Cyber-physical systems; Information security; Sensors (ID#: 15-8691)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7331099&isnumber=7330515

Vani, K.; Gupta, D., "Investigating the Impact of Combined Similarity Metrics and POS Tagging in Extrinsic Text Plagiarism Detection System," in Advances in Computing, Communications and Informatics (ICACCI), 2015 International Conference on, pp. 1578-1584, 10-13 Aug. 2015

doi: 10.1109/ICACCI.2015.7275838

Abstract: Plagiarism is an illicit act which has become a prime concern mainly in educational and research domains. This deceitful act is usually referred as an intellectual theft which has swiftly increased with the rapid technological developments and information accessibility. Thus the need for a system/ mechanism for efficient plagiarism detection is at its urgency. In this paper, an investigation of different combined similarity metrics for extrinsic plagiarism detection is done and it focuses on unfolding the importance of combined similarity metrics over the commonly used single metric usage in plagiarism detection task. Further the impact of utilizing part of speech tagging (POS) in the plagiarism detection model is analyzed. Different combinations of the four single metrics, Cosine similarity, Dice coefficient, Match coefficient and Fuzzy-Semantic measure is used with and without POS tag information. These systems are evaluated using PAN1 -2014 training and test data set and results are analyzed and compared using standard PAN measures, viz, recall, precision, granularity and plagdet_score.

Keywords: fuzzy set theory; industrial property; security of data; text analysis; POS tag information; POS tagging; combined similarity metrics; commonly used single metric usage; cosine similarity; dice coefficient; educational domain; extrinsic plagiarism detection; extrinsic text plagiarism detection system; fuzzy-semantic measure; information accessibility; intellectual theft; match coefficient; part of speech tagging; plagiarism detection model; plagiarism detection task; research domain; standard PAN measure; technological development; Feature extraction; Measurement; Plagiarism; Semantics;Speech; Tagging; Training; Combined Metrics; Extrinsic Plagiarism;POS tagging; Single Metrics; Vector Space Model (ID#: 15-8692)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7275838&isnumber=7275573

Backer, J.; Hely, D.; Karri, R., "On Enhancing the Debug Architecture of a System-on-Chip (Soc) to Detect Software Attacks," in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on, pp. 29-34, 12-14 Oct. 2015. doi: 10.1109/DFT.2015.7315131

Abstract: The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without modifying IP cores. We add hardware components to configure the debug architecture for security monitoring, to store a golden software execution model, and to notify a trusted kernel process when an attack is detected. Our evaluations show that the additions do not impact runtime software execution, and incur 9% area and power overheads on a low-cost processor core.

Keywords: computer debugging; logic circuits; system-on-chip; IP cores; SoC debug architecture enhancement; area overheads; attack detection; hardware components; intellectual property cores; internal logic; low-cost processor core; power overheads; runtime software execution; security monitoring; software attack detection; software execution model; software execution monitoring; software observability; system-on-chip; trusted kernel process; IP networks; Instruments; Monitoring; Registers; Software; Table lookup (ID#: 15-8693)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7315131&isnumber=7315124

Xiaolong Guo; Dutta, R.G.; Jin, Y.; Farahmandi, F.; Mishra, P., "Pre-Silicon Security Verification and Validation: A Formal Perspective," in Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE, pp. 1-6, 8-12 June 2015. doi: 10.1145/2744769.2747939

Abstract: Reusable hardware Intellectual Property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry today. The possibility of hardware Trojans and/or design backdoors hiding in the IP cores has raised security concerns. As existing functional testing methods fall short in detecting unspecified (often malicious) logic, formal methods have emerged as an alternative for validation of trustworthiness of IP cores. Toward this direction, we discuss two main categories of formal methods used in hardware trust evaluation: theorem proving and equivalence checking. Specifically, proof-carrying hardware (PCH) and its applications are introduced in detail, in which we demonstrate the use of theorem proving methods for providing high-level protection of IP cores. We also outline the use of symbolic algebra in equivalence checking, to ensure that the hardware implementation is equivalent to its design specification, thus leaving little space for malicious logic insertion.

Keywords: electronic engineering computing; industrial property; integrated circuit design; integrated circuit testing; security of data; system-on-chip; theorem proving; IP cores protection; PCH; SoC design; equivalence checking; formal methods; functional testing methods; hardware Trojans; hardware trust evaluation; logic insertion; pervasive design; presilicon security validation; presilicon security verification; proof-carrying hardware; reusable hardware intellectual property; system-on-chip design; theorem proving methods; Hardware; IP networks; Logic gates; Polynomials; Sensitivity; Trojan horses (ID#: 15-8694)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7167331&isnumber=7167177

Li Zhang; Chip-Hong Chang, "Public Key Protocol for Usage-Based Licensing of FPGA IP Cores," in Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, pp. 25-28, 24-27 May 2015. doi: 10.1109/ISCAS.2015.7168561

Abstract: Application developers are now turning to field-programmable gate array (FPGA) devices for solutions of small to medium volume due to its post-fabrication flexibility. Unfortunately, the existing upfront intellectual property (IP) licensing model for FPGA based third-party IP cores is economically unattractive. The IP bitstreams in transaction are also vulnerable to cloning, misappropriation and reverse engineering. This paper proposes a secure pay-per-use licensing protocol to avoid complicated communication flow and high implementation cost, while preventing the IP rights from being compromised or abused by all parties involved. The protocol guarantees the confidentiality and integrity of the security-critical components and forbids the implementation of licensed IP cores on gray market or counterfeit chips. The public-crypto based core installation module used to self-configure the licensed IP cores occupies only limited FPGA fabrics temporarily.

Keywords: field programmable gate arrays; logic circuits; microprocessor chips; modules; protocols; public key cryptography; reverse engineering; FPGA IP core; IP bitstream; IP right; counterfeit chip; field programmable gate array; gray market; intellectual property; pay-per-use licensing protocol; post-fabrication flexibility; public key protocol; public-crypto based core installation module; reverse engineering; security critical component; usage-based licensing; Computer integrated manufacturing; Cryptography; Fabrics; Field programmable gate arrays; IP networks; Licenses; Protocols (ID#: 15-8695)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7168561&isnumber=7168553

Konstantinou, C.; Keliris, A.; Maniatakos, M., "Privacy-Preserving Functional IP Verification Utilizing Fully Homomorphic Encryption," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp. 333-338, 9-13 March 2015.  Doi:  (not provided)

Abstract: Intellectual Property (IP) verification is a crucial component of System-on-Chip (SoC) design in the modern IC design business model. Given a globalized supply chain and an increasing demand for IP reuse, IP theft has become a major concern for the IC industry. In this paper, we address the trust issues that arise between IP owners and IP users during the functional verification of an IP core. Our proposed scheme ensures the privacy of IP owners and users, by a) generating a privacy-preserving version of the IP, which is functionally equivalent to the original design, and b) employing homomorphically encrypted input vectors. This allows the functional verification to be securely outsourced to a third-party, or to be executed by either parties, while revealing the least possible information regarding the test vectors and the IP core. Experiments on both combinational and sequential benchmark circuits demonstrate up to three orders of magnitude IP verification slowdown, due to the computationally intensive fully homomorphic operations, for different security parameter sizes.

Keywords: cryptography; data privacy; industrial property; IC design business model; IC industry; IP core; IP reuse; IP theft; IP users; SoC design; fully homomorphic encryption; functional verification; globalized supply chain; intellectual property verification; magnitude IP verification; privacy-preserving functional IP verification; privacy-preserving version; security parameter sizes; sequential benchmark circuits; system-on-chip; Encryption; IP networks; Libraries; Logic gates; Noise (ID#: 15-8696)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7092410&isnumber=7092347

Prashanthi, R., "A Hybrid Fragile High Capacity Watermarking Technique with Template Matching Detection Scheme," in Intelligent Systems and Control (ISCO), 2015 IEEE 9th International Conference on, pp. 1-6, 9-10 Jan. 2015. doi: 10.1109/ISCO.2015.7282332

Abstract: With the rapid growth in the development of digital content, the terms security and privacy are very challenging issues. Watermarking is a broad interesting field which provides way in hiding an informal or formal data in another for maintaining intellectual property rights. The key perspectives of watermarking are security, robustness, invisibility and capacity. In the proposed technique the capacity is increased by embedding two RGB images in one RGB image. The invisibility of the hidden information is obtained by employing least significant bit substitution. The security is enhanced using a novel template matching detection scheme. The proposed fragile watermarking system destroys the watermarks when modified or tampered thus providing integrity and authentication features.

Keywords: image colour analysis; image matching; image watermarking; industrial property; message authentication; RGB image; authentication feature; digital content; fragile watermarking system; hidden information ;high capacity watermarking technique; informal data; intellectual property right; template matching detection scheme; Indexes; Robustness; Watermarking; Fragile; Watermarking; capacity; invisibility; robustness; security (ID#: 15-8697)

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7282332&isnumber=7282219

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