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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
multiprocessing systems
biblio
POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities
Submitted by grigby1 on Thu, 07/16/2020 - 11:18am
Resiliency
Power management
power management algorithms
power management vulnerabilities
power system management
POWERT channel capacity
pubcrawl
representative commercial systems
resilience
power headroom modulation
resource allocation
Runtime
runtime power management
Scalability
Software
system-wide shared resource
tight power budget
application performance requirements
Power demand
power aware computing
multiprocessing systems
Monitoring
microprocessor chips
instantaneous power demand timely
Hardware
critical shared resource
covert communication
covert channels
control systems
Compositionality
composability
channel capacity
bit rate 121.6 bit/s
biblio
Optimization of Hardware-oblivious and Hardware-conscious Hash-join Algorithms on KNL
Submitted by aekwall on Mon, 06/08/2020 - 10:34am
hardware-oblivious hash join algorithms
hash algorithms
parallel computing
multithreading
multicore servers
memory allocation
manycore platforms
KNL hardware characteristics
Knights Landing
hash join
Resiliency
hardware-conscious hash join algorithms
hardware architecture features
algorithm optimization
multi-threading
multiprocessing systems
Compositionality
storage management
parallel processing
pubcrawl
biblio
A Benchmark Suite of Hardware Trojans for On-Chip Networks
Submitted by grigby1 on Fri, 05/15/2020 - 11:45am
Information Leakage
Trojan horses
system-on-chip
standards
side channel analysis
security
Routing
performance degradation
on-chip networks
NoC
network-on-chip
multiprocessing systems
multicore systems
manycore systems
invasive software
network on chip security
HT defense methods
Hardware Trojans
hardware trojan
Hardware
Functional testing
Cryptography
benchmarks
Benchmark testing
benchmark suite
Metrics
Resiliency
resilience
Scalability
biblio
Detecting and Mitigating Low-and-Slow DoS Attacks in NoC-based MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 11:44am
low-and-slow DoS attack
NoC-based MPSoC architectures
NoC-based MPSoC
NoC
network-on-chip
Network on Chip (NoC)
network attack
Muti-Processor System on Chip (MPSoC)
multisource attacks
MultiProcessor Systems-on-Chip
multiprocessing systems
network on chip security
Internet of Things
internet
Distributed Monitoring
denial-of-service attacks
Denial of Service (DoS) Attack
computer network security
Metrics
Resiliency
resilience
Scalability
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 11:44am
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
biblio
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Submitted by grigby1 on Fri, 05/15/2020 - 11:30am
hardware trojan
Trojan horses
system-on-chip
semiconductor design
security
run time mitigation
performance degradation Hardware Trojan attacks
NoC
network-on-chip
multiprocessor system on chips
multiprocessing systems
MPSoC
microprocessor chips
integrated circuit design
performance evaluation
Router Architecture
pubcrawl
hardware security issues
Hardware
denial of service attack
Degradation
Cryptography
cryptographic modules
computer architecture
Buffer storage
bit shuffling mechanism
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 11:30am
programming flexibility
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
microprocessor chips
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
cache location
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
pubcrawl
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
biblio
A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security
Submitted by grigby1 on Fri, 05/15/2020 - 11:30am
manufacturing processes
research hotspots
replay-type hardware Trojan
on-chip systems
NoC vulnerability
NoC power consumption
NoC hardware security
NoC
new hardware logic circuit
network-on-chip
network throughput reduction
multiprocessor chip security
multiprocessing systems
pubcrawl
logic circuits
invasive software
inter-core interconnection method
Integrated circuit interconnections
defense strategies
communication performance optimization
benchmark test set
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 11:29am
Switching circuits
network transmission
network-on-chip
packet switching
packet switching NoC
packet-circuit-switched
security in NoC
Separate interface Hybrid
side-channel attacks
network routing
system security policy
TDM
Throughput
timing
timing channel
timing channel protection
timing characteristics
timing side channel
combined hybrid routers
network on chip security
Scalability
Resiliency
resilience
Metrics
channel attacks
circuit switching
circuit switching NoC
pubcrawl
conventional hybrid router
covert timing channel
hybrid network-on-chip
hybrid NoC
Integrated circuit modeling
MP-SoC
multiprocessing systems
multiprocessor system-on-chip
biblio
Towards the formal verification of security properties of a Network-on-Chip router
Submitted by grigby1 on Fri, 05/15/2020 - 11:29am
IP networks
timing
security
Routing
NoC routing architectures
Network-on-Chip router
network-on-chip
network routing
MultiProcessors Systems-on-Chip
multiprocessing systems
model checking
pubcrawl
integrated circuit design
Hardware
formal verification
Cryptography
Metrics
resilience
Resiliency
Scalability
network on chip security
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