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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Hardware
biblio
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
Submitted by grigby1 on Wed, 09/12/2018 - 11:25am
SIMD
Program processors
Programmable SoC
pubcrawl
real-time on-line pattern search
real-time systems
resilience
Resiliency
Scalability
search problems
platform based design methodologies
string matching
system monitoring
system-on-chip
SystemC
TCP
TCP packets
Xilinx Zynq programmable SoC
Zynq
High-Le'vel Synthesis
Algorithm design and analysis
BM string search algorithm
Boyer-Moore
Boyer-Moore algorithm
computer network security
deep packet inspection
FPGA
Hardware
high level synthesis
Accelerator
high-level synthesis
Inspection
MISD parallelism
Network Monitoring
network security
parallel processing
Payloads
Platform Based Design
biblio
Robust IoT communication physical layer concept with improved physical unclonable function
Submitted by grigby1 on Mon, 06/11/2018 - 3:48pm
Ring Oscillator
Microelectronics Security
Physical Unclonable Function
pubcrawl
PUF
PUF-interfacing communication physical layer hardware
random identification hardware
reliability problems
resilience
Resiliency
Metrics
robust IoT communication physical layer
robust IoT communication physical layer concept
robust monitoring concepts
Robustness
size 65.0 nm
Spectral analysis
suitable physics
tuning
computer network security
Asia
Bandwidth
client-to-cloud communication physical layer
Cloud Computing
cloud-interfacing point
CMOS
CMOS technology
composability
aging
Conferences
generated PUF word
Hardware
hardware concepts
improved physical unclonable function
Internet of Things
IoT concept
IoT-cloud-based communication
biblio
Adaptive models for security and data protection in IoT with Cloud technologies
Submitted by grigby1 on Mon, 06/11/2018 - 3:48pm
Metrics
virtualised sensor nodes
virtual reflection
sensors
sensor-cloud security
sensor-cloud architecture
security
secure association
Resiliency
resilience
Reliability
pubcrawl
Protocols
privacy
multilayer client-server model
Microelectronics Security
adaptive models
IoT
Internet of Things
Hardware
gateways
data storage
Data protection
data privacy
data integrity
computer architecture
composability
cloud technologies
Cloud Computing
authorization
authentication
application servers
biblio
PCH framework for IP runtime security verification
Submitted by grigby1 on Mon, 06/11/2018 - 3:47pm
post-silicon stage
untrusted third-party vendors
untrusted IPs
Trusted Computing
Symbolic Execution
security of data
security
SAT solving methods
runtime formal verification framework
Runtime
Resiliency
resilience
pubcrawl
proof-carrying hardware framework
pre-silicon stage
composability
PCH framework
Microelectronics Security
Metrics
Mathematical model
malicious behavior detection
IP runtime security verification
integrated circuits
high-level security assurance
hardware runtime verification
Hardware design languages
Hardware
Foundries
formal verification
biblio
Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants
Submitted by grigby1 on Mon, 06/11/2018 - 3:37pm
SD-card storage manager
Named Data Network Security
open-source designs
pattern classification
program debugging
program verification
pubcrawl
Registers
resilience
Resiliency
robotics controller
Scalability
Local area networks
security
security of data
sequential logic
SIMAREL
specification languages
storage management
STREAMS policies
unbounded input streams
user interfaces
Wires
Ethernet controller
automatically-synthesized relational invariants
circuit executions
core design C
debugging interface
declassification
digital signal processing chips
digital-signal processing module
Domain-Specific Language
DSP module
dynamic conditions
Algorithm design and analysis
field programmable gate arrays
flash memories
flash memory controller
flow security
Hardware
Hardware design languages
Human behavior
human computer interaction
information leaks
information-flow policies
biblio
Minimum energy quantized neural networks
Submitted by grigby1 on Mon, 06/11/2018 - 3:24pm
iso-accuracy depending
automated minimum-energy optimization
BinaryNets
complex arithmetic
fixed point arithmetic
fundamental trade-off
generic hardware platform
higher precision operators
int4 implementations
int8 networks
arbitrary fixed point precision
low precision weights
Minimum Energy
minimum energy QNN
QNN training
Quantized Neural Network
quantized neural networks
wider network architectures
network on chip security
resilience
Resiliency
Scalability
Hardware
neural nets
energy consumption
telecommunication security
Neural networks
Training
deep learning
pubcrawl
Memory management
Metrics
Random access memory
system-on-chip
energy conservation
power aware computing
Mobile communication
approximate computing
biblio
PUFSec: Protecting physical unclonable functions using hardware isolation-based system security techniques
Submitted by grigby1 on Mon, 06/11/2018 - 3:20pm
physical unclonable function protection
Xilinx SoC
system-on-chip
system security techniques
Software
security protection
security policies
security compromises
security challenges
secure architecture extension
Resiliency
resilience
PUFSec framework
PUF workflow
PUF hardware
pubcrawl
Access Control
Networked Control Systems Security
Monitoring
Modeling Attacks
Metrics
internal PUF design
hardware isolation
Hardware
DoS attacks
Denial of Service attacks
Data protection
control systems
computer network security
computer architecture
composability
ARM Processor
biblio
SRAM voltage scaling for energy-efficient convolutional neural networks
Submitted by grigby1 on Thu, 06/07/2018 - 3:06pm
Si
memory power intensive
memory size 8 KByte
Micromechanical devices
neural nets
Neural Network Resilience
pubcrawl
Random access memory
resilience
Resiliency
low-power embedded system
Silicon
silicon-on-insulator
size 28 nm
SRAM chips
SRAM voltage scaling
Training
UTBB FD-SOI CMOS
voltage 310 mV
energy-efficient convolutional neural network
bit error injection
Bit error rate
CMOS memory circuits
ConvNet training
convolutional neural networks
deep learning
electronic engineering computing
elemental semiconductors
energy conservation
approximate SRAM
energy-quality tradeoff
error resiliency
floating-point classification accuracy
Hardware
Hardware Implementation
IoE platform
learning (artificial intelligence)
low-power electronics
biblio
An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations
Submitted by grigby1 on Thu, 06/07/2018 - 3:06pm
natural language processing
timing
temperature variations
Speech recognition
Resiliency
resilience
pubcrawl
problem solving
Neural Network Resilience
neural network algorithms
neural nets
adders
multilayer perceptrons
MLP
medical applications
Logic gates
learning (artificial intelligence)
hardware neural networks
Hardware
dynamic voltage
CNN
Biological neural networks
biblio
A red team blue team approach towards a secure processor design with hardware shadow stack
Submitted by grigby1 on Thu, 06/07/2018 - 3:02pm
private data access
Trusted Computing
software attacks
security of data
security
RISC-V
return oriented programming attack
Resiliency
resilience
reduced instruction set computing
red team blue team approach
pubcrawl
processor vulnerabilities
processor design security
processor architecture
composability
Payloads
openrisc
open processor architectures
object-oriented programming
object oriented security
Metrics
memory corruption
hardware-software codesign
hardware shadow stack
Hardware
embedded systems
embedded system security
Computer bugs
computer architecture
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