| Title | FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption |
| Publication Type | Conference Paper |
| Year of Publication | 2016 |
| Authors | Srinivas, N. S. S., Akramuddin, M. |
| Conference Name | 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) |
| Keywords | advanced encryption standard (AES), AES Rijndael algorithm, AES-128, AES-192, AES-256, Algorithm design and analysis, algorithmic functions, Clocks, composability, cryptography, decryption, Encryption, Field Programmable Gate Array (FPGA), field programmable gate arrays, FPGA based hardware implementation, Galois field multiplications, Galois fields, GF (28), Hardware Description Language (HDL), hardware description languages, inverse mix-columns transformations, Inverse S-Box transformations, network on chip, network on chip security, network security algorithm, pre-calculated look-up tables, precalculated LUT, pubcrawl, Resiliency, Rijndael, Scalability, secure data transmission, Table lookup, Timing, Verilog-HDL, Virtex-7 XC7VX690T chip, wired digital communication networks, wireless digital communication networks, Xilinx ISE Design Suite-14.7 Tool, Xilinx Virtex-7 FPGA, Xilinx XPower Analyzer |
| Abstract | AES algorithm or Rijndael algorithm is a network security algorithm which is most commonly used in all types of wired and wireless digital communication networks for secure transmission of data between two end users, especially over a public network. This paper presents the hardware implementation of AES Rijndael Encryption and Decryption Algorithm by using Xilinx Virtex-7 FPGA. The hardware design approach is entirely based on pre-calculated look-up tables (LUTs) which results in less complex architecture, thereby providing high throughput and low latency. There are basically three different formats in AES. They are AES-128, AES-192 and AES-256. The encryption and decryption blocks of all the three formats are efficiently designed by using Verilog-HDL and are synthesized on Virtex-7 XC7VX690T chip (Target Device) with the help of Xilinx ISE Design Suite-14.7 Tool. The synthesis tool was set to optimize speed, area and power. The power analysis is made by using Xilinx XPower Analyzer. Pre-calculated LUTs are used for the implementation of algorithmic functions, namely S-Box and Inverse S-Box transformations and also for GF (28) i.e. Galois Field Multiplications involved in Mix-Columns and Inverse Mix-Columns transformations. The proposed architecture is found to be having good efficiency in terms of latency, throughput, speed/delay, area and power. |
| DOI | 10.1109/ICEEOT.2016.7754990 |
| Citation Key | srinivas_fpga_2016 |
FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption