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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Resiliency
biblio
Discovering Insider Threats from Log Data with High-Performance Bioinformatics Tools
Submitted by grigby1 on Thu, 04/20/2017 - 11:42am
Anomaly Detection
Damage Assessment
insider threat
log data clustering
Network reconnaissance
outlier detection
pubcrawl
Resiliency
biblio
Cyber Deception: Virtual Networks to Defend Insider Reconnaissance
Submitted by grigby1 on Thu, 04/20/2017 - 11:42am
advanced persistent threat
insider reconnaissance
insider threat
Network reconnaissance
network security
pubcrawl
Resiliency
software defined networking
biblio
A flexible system-on-a-chip implementation of the Advanced Encryption Standard
Submitted by grigby1 on Thu, 04/20/2017 - 11:41am
network on chip
Xilinx Zynq 7000
system-on-chip
System-on-a-chip
symmetric encryption
standards
security
Scalability
resource usage
Resiliency
Registers
pubcrawl
processor
peripheral interfaces
network security
network on chip security
advanced encryption standard
hardware-software approach
flexible system-on-a-chip
flexible interface
field programmable gate arrays
encryption algorithm
encryption
Cryptography
composability
complex electronic systems
Clocks
cipher block chaining mode
CBC
AES
advanced peripheral bus
biblio
A high speed implementation counter mode cryptography using hardware parallelism
Submitted by grigby1 on Thu, 04/20/2017 - 11:41am
parallel computing
hardware parallelism
Heracles toolkit
high speed implementation counter mode cryptography
network-on-chip
network on chip
Network on Chip(NoC)
network on chip security
NoC
graphics processing units
pubcrawl
Resiliency
Scalability
secure data transmission
security mechanisms
Software algorithms
unsecured networks
DES
Big Data
composability
Counter Mode Cryptography (CTR)
CPU
Cryptography
CTR
data encryption standard core
Data Encryption Standard (DES)
Algorithm design and analysis
encryption
field programmable gate arrays
FPGA
FPGA board
gpu
Grafic Process Unite(GPU)
graphics processing unit
biblio
Analog cellular neural network for application in physical unclonable functions
Submitted by grigby1 on Thu, 04/20/2017 - 11:41am
Resiliency
Monte Carlo simulation
network on chip
network on chip security
neural chips
Physically Unclonable Function (PUF)
physical unclonable function design
process variation
pubcrawl
PUF instances
Monte Carlo methods
Scalability
secret key generation
Semiconductor device modeling
size 45 nm
Trajectory
unclonable core module
unpolarized Gaussian-shaped distribution
word length 100 bit
CMOS technology
analogue circuits
cellular neural nets
Cellular Neural Network (CNN)
Cellular neural networks
challenge-response security system
circuit dynamical behavior
CMOS analogue integrated circuits
CMOS integrated circuits
analog cellular neural network
composability
Cryptography
device identification-authentication
Hamming distance
Hardware
Hardware Security
integrated circuit design
Integrated circuit modeling
biblio
A system-level security approach for heterogeneous MPSoCs
Submitted by grigby1 on Thu, 04/20/2017 - 11:41am
system-level security approach
Scalability
security
Access Control
complex embedded systems
composability
shared IP
direct memory access
dynamic permissions configuration
embedded systems
Hardware
heterogeneous execution platforms
heterogeneous hardware platforms
heterogeneous MPSoC
shared libraries
Resiliency
IP networks
isolation
memory access
memory transactions
multiprocessing systems
multiprocessor
network on chip
network on chip security
Program processors
prototype isolation unit
pubcrawl
system-on-chip
real-time systems
biblio
FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption
Submitted by grigby1 on Thu, 04/20/2017 - 11:40am
secure data transmission
Inverse S-Box transformations
network on chip
network on chip security
network security algorithm
pre-calculated look-up tables
precalculated LUT
pubcrawl
Resiliency
Rijndael
Scalability
inverse mix-columns transformations
Table lookup
timing
Verilog-HDL
Virtex-7 XC7VX690T chip
wired digital communication networks
wireless digital communication networks
Xilinx ISE Design Suite-14.7 Tool
Xilinx Virtex-7 FPGA
Xilinx XPower Analyzer
decryption
AES-128
AES-192
AES-256
AES Rijndael algorithm
Algorithm design and analysis
algorithmic functions
Clocks
composability
Cryptography
advanced encryption standard (AES)
encryption
Field Programmable Gate Array (FPGA)
field programmable gate arrays
FPGA based hardware implementation
Galois field multiplications
Galois fields
GF (28)
Hardware Description Language (HDL)
hardware description languages
biblio
Hardware security assurance in emerging IoT applications
Submitted by grigby1 on Thu, 04/20/2017 - 11:40am
IoT connected devices
Trojan horses
thwart hardware Trojan attack
side-channel analysis attack
Security Assurance
Scalability
Resiliency
Radiation detectors
pubcrawl
network on chip security
network on chip
network-on-chip
low-cost dynamic permutation method
IoT processing unit
accumulated partial guessing entropy
invasive software
Internet-of-Things (IoT)
Internet of Things
hardware trojan
hardware security assurance
Hardware Security
hardware attacks
Hardware
Cryptography
computation power
composability
Cisco
biblio
Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs
Submitted by grigby1 on Thu, 04/20/2017 - 11:40am
3D ICs
composability
Hardware Security
network on chip
network on chip security
network-on-chip
pubcrawl
Resiliency
Scalability
trojan horse detection
biblio
Lightweight secure sensing using hardware isolation
Submitted by grigby1 on Thu, 04/20/2017 - 11:40am
network on chip security
Xilinx Zynq-7000 SoC leveraging ARM TrustZone
wireless sensor networks
Temperature sensors
system-on-chip
security of data
Scalability
Resiliency
pubcrawl
composability
network on chip
Monitoring
lightweight secure sensing technique
hardware isolation
Hardware
delays
Cryptography
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