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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
NoC
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
biblio
Test methodology for detecting short-channel faults in network on- chip networks using IOT
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
integrated circuit reliability
short-channel fault detection
Routing
routers networks
Power demand
NoC
network-on-chip analysis machine
network-on-chip
network routing
network on- chip networks
network on chip
Monitoring
IoT
Internet of Things
interconnection networks
integrated circuit testing
network on chip security
Integrated circuit interconnections
fault diagnosis
Encoders/decoders
Data Security
Data protection
data encryption
Cryptography
Conferences
computing-intensive data processing
computer architecture
Aerospace electronics
Metrics
Resiliency
resilience
Scalability
biblio
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
hardware trojan
Trojan horses
system-on-chip
semiconductor design
security
run time mitigation
performance degradation Hardware Trojan attacks
NoC
network-on-chip
multiprocessor system on chips
multiprocessing systems
MPSoC
microprocessor chips
integrated circuit design
performance evaluation
Router Architecture
pubcrawl
hardware security issues
Hardware
denial of service attack
Degradation
Cryptography
cryptographic modules
computer architecture
Buffer storage
bit shuffling mechanism
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
programming flexibility
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
microprocessor chips
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
cache location
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
pubcrawl
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
biblio
A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
manufacturing processes
research hotspots
replay-type hardware Trojan
on-chip systems
NoC vulnerability
NoC power consumption
NoC hardware security
NoC
new hardware logic circuit
network-on-chip
network throughput reduction
multiprocessor chip security
multiprocessing systems
pubcrawl
logic circuits
invasive software
inter-core interconnection method
Integrated circuit interconnections
defense strategies
communication performance optimization
benchmark test set
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Secure Network-on-Chip Architectures for MPSoC: Overview and Challenges
Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm
multiprocessing systems
Trojan horses
security threat attacks
security
secure routing algorithms
secure routing algorithm
secure network-on-chip architectures
Routing
processing cores
NoC-based systems
NoC
network-on-chip
multiprocessor-based systems on chip
pubcrawl
MPSoC
Malicious-Tolerant Routing Algorithms
HT
hardware trojan
Hardware
data communication
computer architecture
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Analysis of Black Hole Router Attack in Network-on-Chip
Submitted by grigby1 on Mon, 03/23/2020 - 4:15pm
Resiliency
Multiprocessors System-on-Chip
network-on-chip
network on chip security
NoC
outsourcing
outsourcing design
Packet loss
processing cores
pubcrawl
resilience
multiprocessing systems
Router Systems Security
Scalability
security
security attacks
sensitive information
System performance
telecommunication network routing
Trojan horses
very strong violent attack
Hardware
BHR attack
Black Hole Router attack
black holes
Blak Hole
communication platform
computer network security
data packets
denial of service attack
Denial-of-Service
DoS.
BHR
hardware trojan
HT
HT model
infected node
Integrated circuit modeling
invasive software
malicious Hardware Trojan
malicious nodes
Metrics
biblio
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers
Submitted by grigby1 on Mon, 11/04/2019 - 12:39pm
NoC
Trojan horses
system-on-chip
System recovery
security attacks
security
secure routing algorithm
secret key leaking
runtime detection
Runtime
Routing
Router Systems Security
Resiliency
resilience
pubcrawl
outsourcing
network on chip security
network-on-chip architecture
network-on-chip
network routing
Multiprocessors System-on-Chip
multiprocessing systems
MPSoC
Metrics
Malicious-tolerant Routing Algorithm
malicious Hardware Trojans
logic design
invasive software
integrated circuits
hardware trojan
Hardware
biblio
A security-aware routing implementation for dynamic data protection in zone-based MPSoC
Submitted by grigby1 on Mon, 06/11/2018 - 3:24pm
multiprocessing systems
network on chip security
Zones
security-aware routing
network-on-chip routing
network routing
multiprocessor system-on-chip
MPSoC
Encapsulation
asymmetrical security zones
Firewalls (computing)
Runtime
NoC
Routing protocols
Metrics
resilience
Routing
IP networks
Data protection
network-on-chip
Scalability
Resiliency
pubcrawl
security
biblio
A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture
Submitted by grigby1 on Wed, 05/09/2018 - 2:47pm
on-chip component
verification
UVM
Universal Verification Methodology
traffic control
Throughput
system-on-chip
standardized methodology
scalable verification
Scalability
reusable methodology
Resiliency
resilience
reconfigurable verification
pubcrawl
benchmark
Object oriented modeling
NoC
network-on-chip architecture
network-on-chip
Monitoring
Metrics
interconnection architectures
integrated circuit design
Generators
Compositionality
complex on-chip communication problems
Benchmark testing
benchmark environment
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