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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
logic circuits
biblio
MUTARCH: Architectural diversity for FPGA device and IP security
Submitted by grigby1 on Tue, 01/23/2018 - 2:24pm
policy-based governance
IP security
logical configuration keys
logic circuits
microprocessor chips
modern remote upgrade techniques
MUTARCH
physical configuration keys
Policy
IP piracy
pubcrawl
Resiliency
security through diversity principle
static keys
Table lookup
time-varying keys
Transforms
unauthorized in-field reprogramming
field programmable gate arrays
automotive systems
biomedical systems
bitstream encryption
collaboration
composability
configuration file
diverse applications
encryption
architectural diversity
FPGA device
Hardware
in-field reconfiguration
intellectual property blocks
Internet of Things
IoT
IP blocks
biblio
Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks
Submitted by grigby1 on Tue, 01/23/2018 - 2:24pm
Logic gates
Training data
TBS
Support vector machines
security
Reversible logic
reversible circuit synthesis approaches
Resiliency
QMDD
pubcrawl
policy-based governance
Policy
network synthesis
machine learning algorithms
machine learning
BDD
logic design
logic circuits
learning (artificial intelligence)
IP piracy attacks
IP piracy
Interference
integrated circuit piracy
Integrated circuit modeling
industrial property
ESOP
embedded function
composability
collaboration
biblio
Recovery-based resilient latency-insensitive systems
Submitted by BrandonB on Wed, 05/06/2015 - 1:53pm
logic circuits
Throughput
System performance
synchronous circuits
Synchronization
stalling signal
RLIS
Relays
recovery-based resilient latency-insensitive systems
queue sizing problem
clock cycle time
interconnect delay
Integrated circuit interconnections
improved queues
global stalling mechanism
expensive timing cost
error-recovery
error impact
Degradation
Clocks
biblio
Slack removal for enhanced reliability and trust
Submitted by BrandonB on Wed, 05/06/2015 - 10:34am
Small Delay Defects
mission-critical application
pattern count
reliability enhancement
security of data
security vulnerabilities
security-critical application
slack removal
Slacks
malicious circuitries
test quality
testing
timing slacks
transition fault patterns
Trojan horses
trust enhancement
Wires
fabrication
care bit density intact
Circuit faults
delay defect detection
delay defects
delay unit insertion
delays
design for testability
design technique
At-speed Testing
Hardware
hardware trojan
Hardware Trojans
integrated circuit reliability
logic circuits
Logic gates
logic testing
biblio
Detection of hardware Trojan in SEA using path delay
Submitted by BrandonB on Wed, 05/06/2015 - 10:33am
HTH detection and insertion
Trojan horses
Trojan circuits
SEA crypto
scalable encryption algorithm crypto
Scalable Encryption Algorithm (SEA)
payload Trojan detection rate
payload Trojan
path delay
Logic gates
logic circuits
layout level Trojan insertions
IP blocks
invasive software
Algorithm design and analysis
hardware Trojan horses insertion
Hardware Trojan horses (HTH)
hardware Trojan detection
Hardware
GDSII hard macros
GDSII
gate level Trojan insertions
fabless design house
encryption
delays
Cryptography
ASIC design flow
application specific integrated circuits
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