logic circuits

biblio

Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience

Submitted by grigby1 on Tue, 10/06/2020 - 12:40pm

dynamic adaptation
Resiliency
resilience
quantitative error resilience
pubcrawl
Power demand
power consumption
power aware computing
Neurons
logic circuits
Hardware
error resilience
dynamic adaptation of approximate bit-width
adders
convolutional neural networks
convolutional neural network
convolutional neural nets
convolution
configurable adder
Computing Theory
CNNs
approximation theory
approximate computing technology
approximate computing
approximate bit-width

biblio

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access

Submitted by aekwall on Tue, 09/08/2020 - 8:59am

locked circuits
Chained Attacks
working chip
unauthorized scan access
secret key recovery
scan chain
SAT attack
robust DFS technique
robust DFS design
robust design-for-security architecture
restricted scan chain access
logic locking security
logic locking attacks
Scalability
IP piracy
Boolean satisfiability based attack
benchmark circuits
ATPG
Boolean functions
logic circuits
computability
Security analysis
logic locking
pubcrawl
Resiliency
Cryptography

biblio

Reusable intellectual property core protection for both buyer and seller

Submitted by grigby1 on Thu, 07/30/2020 - 1:05pm

intellectual property
seller watermark
scheduling phase
reusable intellectual property core protection
register allocation phase
latency overhead
IP seller
IP core protection
IP core design
design cost overhead
Consumer electronics
CE devices
buyer fingerprint
architectural synthesis process
ip protection
Watermarking
logic circuits
resource management
Metrics
Fingerprint recognition
Registers
composability
embedded systems
microprocessor chips
Resiliency
resilience
policy-based governance
Human Factors
Human behavior
pubcrawl
IP networks
logic design

biblio

A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security

Submitted by grigby1 on Fri, 05/15/2020 - 11:30am

manufacturing processes
research hotspots
replay-type hardware Trojan
on-chip systems
NoC vulnerability
NoC power consumption
NoC hardware security
NoC
new hardware logic circuit
network-on-chip
network throughput reduction
multiprocessor chip security
multiprocessing systems
pubcrawl
logic circuits
invasive software
inter-core interconnection method
Integrated circuit interconnections
defense strategies
communication performance optimization
benchmark test set
Metrics
resilience
Resiliency
Scalability
network on chip security

biblio

Resolving the Trilemma in Logic Encryption

Submitted by grigby1 on Fri, 04/03/2020 - 11:56am

post SAT approaches
trilemma
traditional logic encryption algorithms
structural security
SAT attack
Resiliency
resilience
query complexity
pubcrawl
provable security
provable logic obfuscation
pre-SAT approaches
Compositionality
Metrics
logic resynthesis
logic design
logic circuits
locking robustness
locked circuit
hardware ip protection
error number
encryption efficiency
Cryptography
computability

biblio

Optimizing Quantum Circuits for Modular Exponentiation

Submitted by aekwall on Mon, 01/20/2020 - 10:48am

pubcrawl
verilog implementation
tools
scalable synthesis methods
Scalability
reversible modular exponentiation function
Resiliency
Qubit
Quantum error correction
Quantum Error Correcting Codes (QECC)
quantum computing
quantum computers
quantum circuits
quantum architectures
Quantum Algorithm(QA)
computer architecture
modular exponentiation functions
modular exponentiation
Logic gates
logic designs
logic design
logic circuits
linear nearest neighbor property
Linear Nearest Neighbor (LNN)
Hardware design languages
hardware description languages
exponentiation functions
exponentiation
error correction

biblio

SIMULATION OF QUANTUM ENCODER DECODER WITH FLIP BIT ERROR CORRECTION USING REVERSIBLE QUANTUM GATES

Submitted by grigby1 on Tue, 10/08/2019 - 3:42pm

QEC
security
Scalability
reversible quantum gates
Resiliency
resilience
Quantum technology
quantum noise
quantum information
quantum gates
Quantum error correction
quantum encoder & decoder
quantum cryptography
quantum computing security
quantum computing
Quantum circuit
composability
QCAD
pubcrawl
Metrics
Logic gates
logic circuits
Integrated circuit modeling
flip bit error correction
faulty quantum gates
fault-tolerant quantum computation
error correction codes
error correction
Decoding
Computational modeling
computation process

biblio

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation

Submitted by grigby1 on Fri, 03/15/2019 - 10:58am

invasive software
Tunneling magnetoresistance
Trojan horses
trojan horse detection
Thwart Hardware Trojan insertion
Sensitivity
security of data
pubcrawl
prevention methods
original circuit
novel prevention technique
malicious modifications
logic circuits
ad-hoc design rules
integrated circuits
integrated circuit industry
Hardware Trojans
hardware trojan
Hardware
fabricated IC
error detection
critical circuits
Circuit faults
approximation
approximate logic circuit

biblio

Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

Submitted by grigby1 on Mon, 06/11/2018 - 2:48pm

processed data
Metrics
Microelectronics Security
PAA
power analysis attacks
power consumption
Power dissipation
private key cryptography
probability
Probability distribution
low-power electronics
pubcrawl
resilience
Resiliency
secret cryptographic keys
secured dual-rail-precharge mux
side channel attack
Signal to noise ratio
Switches
DPMUX symmetric-logic
average power dissipation
clock cycle
combinatorial logic
composability
cryptographic algorithms
Cryptography
delays
deterministic power
Digital circuits
activity factor
dynamic switching energy
Hardware implementations
Information Leakage
linear relationship
logic circuits
logic design
Logic gates
low voltage applications

biblio

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection

Submitted by grigby1 on Wed, 04/11/2018 - 1:59pm

Sensitivity
logic testing
Power based Side-channel
Power measurement
probability
process variation levels
Process Variations
pubcrawl
relative power difference
resilience
Resiliency
logic circuits
sequential type Trojans
side channel analysis
spatial correlation
Systematics
test pattern generation
Trojan activation probability
trojan horse detection
Trojan horses
Trojan inserted circuits
hardware trojan
automatic test pattern generation
combinational type Trojans
composability
cyber physical systems
delays
Detection sensitivity
efficient Trojan detection approach
elevated process variations
Hardware
AES-128 circuit
hardware Trojan detection
high detection sensitivity
integrated circuit design
integrated circuit testing
integrated circuits
intra-die-variation
invasive software
ISCAS 89 benchmark
ITC 99 benchmark

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Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

logic circuits

Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access

Reusable intellectual property core protection for both buyer and seller

A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security

Resolving the Trilemma in Logic Encryption

Optimizing Quantum Circuits for Modular Exponentiation

SIMULATION OF QUANTUM ENCODER DECODER WITH FLIP BIT ERROR CORRECTION USING REVERSIBLE QUANTUM GATES

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation

Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection