Visible to the public Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

TitleSecured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications
Publication TypeConference Paper
Year of Publication2017
AuthorsZabib, D. Z., Levi, I., Fish, A., Keren, O.
Conference Name2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Date Publishedoct
ISBN Number978-1-5386-3766-1
Keywordsactivity factor, average power dissipation, clock cycle, combinatorial logic, composability, cryptographic algorithms, cryptography, delays, deterministic power, Digital circuits, DPMUX symmetric-logic, dynamic switching energy, Hardware implementations, information leakage, linear relationship, logic circuits, logic design, Logic gates, low voltage applications, low-power electronics, Metrics, Microelectronics Security, PAA, power analysis attacks, power consumption, Power dissipation, private key cryptography, probability, Probability distribution, processed data, pubcrawl, resilience, Resiliency, secret cryptographic keys, secured dual-rail-precharge mux, side channel attack, Signal to noise ratio, Switches
Abstract

Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: Ptot(t) = a * (Pd(t) + Ppvt(t)) (1) where a is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. Pd is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. Ppvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) a and Pd.

URLhttps://ieeexplore.ieee.org/document/8309254/
DOI10.1109/S3S.2017.8309254
Citation Keyzabib_secured_2017