logic design

biblio

FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

Submitted by aekwall on Mon, 11/09/2020 - 12:31pm

logic design
ring oscillator physical unclonable function
ring oscillator based physical unclonable function
Ring Oscillator
Resiliency
PUF
pubcrawl
policy-based governance
Oscillators
logic obfuscation
Logic gates
composability
IP piracy
IP obfuscation
hardware obfuscation
FPGA IP obfuscation
FPGA based IP protection scheme
FPGA based designs
FPGA
field programmable gate arrays
Cryptography

biblio

IC/IP Piracy Assessment of Reversible Logic

Submitted by aekwall on Mon, 11/09/2020 - 12:31pm

proper-size reversible functions
BDD
binary decision diagrams
embedded function
garbage outputs
IC-IP piracy assessment
IC/IP piracy
intellectual property piracy
Number of embeddings
ancillary inputs
QMDD
quantum multivalued decision diagrams
regular functions
Reversible logic
reversible logic circuits
reversible logic synthesis tools
IP piracy
IP networks
adiabatic computing
logic design
logic circuits
adders
Integrated circuit modeling
industrial property
Logic gates
quantum computing
Trojan horses
policy-based governance
composability
pubcrawl
Resiliency
embedded systems
security

biblio

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints

Submitted by grigby1 on Mon, 11/02/2020 - 12:36pm

pubcrawl
two-stage performance-constrained task scheduling algorithm
Trojan horses
task scheduling
Task Analysis
system-on-chip
System performance
system level security constraints
security-driven task scheduling
security of data
security
scheduling
Schedules
schedule length
Resiliency
resilience
composability
Processor scheduling
policy-based governance
performance constraints
Multiprocessor System-on-Chips
multiprocessing systems
MPSoC
malicious inclusions
logic design
IP networks
intellectual property security
industrial property
hardware trojan
Hardware
graph theory
delays

biblio

Identification of State Registers of FSM Through Full Scan by Data Analytics

Submitted by grigby1 on Fri, 08/28/2020 - 2:55pm

industrial property
state transitions
state register identification
Silicon
Scalability
Resiliency
resilience
regression analysis
Registers
pubcrawl
Physical design
OpenCores
logic design
Intellectual Property Protection
Big Data
FSM state registers
FSM design
finite-state machine
finite state machines
electronic engineering computing
downstream design
Decision trees
Decision Tree
Data protection
Data mining
data analysis
big data security metrics
Big Data Analytics

biblio

Automated Synthesis of Differential Power Attack Resistant Integrated Circuits

Submitted by aekwall on Mon, 08/24/2020 - 11:41am

Dynamic Differential Logic
cryptographic processors
cryptographic systems
differential circuit design
differential logic
Differential Power Analysis
differential power analysis attacks
differential power attack resistant integrated circuits
DPA attack resistance
DPA resistant cell designs
combinational cells
fully automated synthesis system DPA resistant integrated circuits
MDPL
multiplying circuits
RT level Verilog specifications
secret key information
Secure Differential Multiplexer Logic
sequential cells
sequential circuits
power consumption
Resiliency
pubcrawl
composability
Cryptography
standards
tools
Libraries
Automated Response Actions
Logic gates
private key cryptography
Power demand
logic design
Hardware Security
Resistance
combinational circuits
Automated Synthesis
CMOS logic circuits
CMOS synthesis

biblio

Reusable intellectual property core protection for both buyer and seller

Submitted by grigby1 on Thu, 07/30/2020 - 1:05pm

intellectual property
seller watermark
scheduling phase
reusable intellectual property core protection
register allocation phase
latency overhead
IP seller
IP core protection
IP core design
design cost overhead
Consumer electronics
CE devices
buyer fingerprint
architectural synthesis process
ip protection
Watermarking
logic circuits
resource management
Metrics
Fingerprint recognition
Registers
composability
embedded systems
microprocessor chips
Resiliency
resilience
policy-based governance
Human Factors
Human behavior
pubcrawl
IP networks
logic design

biblio

A New Pay-Per-Use Scheme for the Protection of FPGA IP

Submitted by grigby1 on Thu, 07/30/2020 - 12:53pm

complex FPGA designs
ip protection
reusable intellectual property design blocks
Physical Unclonable Function
pay-per-use
IP instance
IP infringement
FSM
FPGA IP vendor
FPGA IP protection
finite state machine
Field-Programmable Gate Arrays
Design methodology
copy protection
logic design
application specific integrated circuits
finite state machines
Licenses
composability
PUF
industrial property
field programmable gate arrays
Resiliency
resilience
policy-based governance
pubcrawl
IP networks
security

biblio

Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs

Submitted by grigby1 on Fri, 07/03/2020 - 12:26pm

resilience
virtual platforms
virtual platform
transaction level modeling
TLM
time-varying systems
time-domain analysis
system-on-chip FPGA
system-on-chip
system on chip
Software
search engines
Scalability
Resiliency
computer architecture
pubcrawl
Mentor Vista
logic design
Inspection
hybrid CPU/FPGA
hardware-IP based architecture
hardware accelerators
Hardware
field programmable gate arrays
ESL
deep packet inspection
CPU-DMA based architecture

biblio

SigAttack: New High-level SAT-based Attack on Logic Encryptions

Submitted by aekwall on Mon, 04/06/2020 - 9:06am

DIP-generation attack
pattern locks
SigAttack
SAT-resilient encryptions
piracy
logic encryption design
key-revealing signature
high-level SAT-based attack
hardware protection technique
Electronics packaging
distinguishing input pattern generation
Scalability
Error analysis
logic design
Logic gates
Complexity theory
attacks
pubcrawl
Human behavior
Resiliency
Hardware
Cryptography

biblio

Resolving the Trilemma in Logic Encryption

Submitted by grigby1 on Fri, 04/03/2020 - 11:56am

post SAT approaches
trilemma
traditional logic encryption algorithms
structural security
SAT attack
Resiliency
resilience
query complexity
pubcrawl
provable security
provable logic obfuscation
pre-SAT approaches
Compositionality
Metrics
logic resynthesis
logic design
logic circuits
locking robustness
locked circuit
hardware ip protection
error number
encryption efficiency
Cryptography
computability

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Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

logic design

FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function

IC/IP Piracy Assessment of Reversible Logic

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints

Identification of State Registers of FSM Through Full Scan by Data Analytics

Automated Synthesis of Differential Power Attack Resistant Integrated Circuits

Reusable intellectual property core protection for both buyer and seller

A New Pay-Per-Use Scheme for the Protection of FPGA IP

Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs

SigAttack: New High-level SAT-based Attack on Logic Encryptions

Resolving the Trilemma in Logic Encryption