logic design

biblio

Resilient Reorder Buffer Design for Network-on-Chip

Submitted by grigby1 on Fri, 03/27/2020 - 10:27am

Reorder Buffer
Network interfaces
network-on-chip
Network-on-Chip Advanced eXtensible Interface Network Interface block
parallel processing
policy-based governance
pubcrawl
random control logic
Registers
Metrics
resilience
Resiliency
resilient Reorder buffer design
Safe Coding
safe control logic design
safe ROB design
Safety
Table lookup
fault tolerance
buffer circuits
collaboration
control logic function
Diagnostic Coverage requirement
error correction codes
error detection
error detection code
error detection codes
area efficient safe design techniques
Fault tolerant systems
high performance computing systems
Human behavior
Human Factors
Industries
integrated circuit design
invariance checking
logic design

biblio

Special Session: Countering IP Security Threats in Supply Chain

Submitted by grigby1 on Thu, 03/12/2020 - 11:09am

Monitoring
Valves
Trojan insertion
Training
telecommunication security
tagging
supply chain security
supply chain management
Supply Chain
Scalability
reverse engineering
Resiliency
resilience
pubcrawl
Protocols
production engineering computing
Data models
machine learning
logic locking schemes
logic design
learning-based trust verification
learning (artificial intelligence)
IP security threats
invasive software
internet
integrated circuits
integrated circuit technology
integrated circuit manufacture
integrated circuit fabrication
integrated circuit design
Human behavior
electronic engineering computing

biblio

Increasing the SAT Attack Resiliency of In-Cone Logic Locking

Submitted by grigby1 on Wed, 02/26/2020 - 3:48pm

Logic gates
security
satisfiability attack
SAT attack resiliency
SAT attack
Resiliency
resilience
removal attack
pubcrawl
MFFC based algorithm
maximum fanout free cones
manufacturing
logic locking
provable security
logic design
key gate selection
Iterative methods
integrated logic circuits
integrated circuits
in-cone techniques
in-cone logic locking
Hardware Security
Hardware
Electronics packaging
circuit netlist

biblio

Hardware Trojan Insertion and Detection in Asynchronous Circuits

Submitted by grigby1 on Wed, 02/26/2020 - 3:38pm

neural network
Trojan horses
trojan horse detection
Trojan detection methods
synchronous hardware Trojan
supply chain security
Routing
Resiliency
resilience
Random Forest
pubcrawl
Pipelines
asynchronous circuit
logic design
Latches
hardware Trojan threats
hardware Trojan insertion
hardware trojan
Hardware
delays
deep learning
cyber physical systems
asynchronous hardware Trojan circuits
asynchronous circuits

biblio

Research in Fast Modular Exponentiation Algorithm Based on FPGA

Submitted by grigby1 on Tue, 01/21/2020 - 10:50am

Montgomery algorithm
systolic arrays
systolic array
Scalability
Resiliency
resilience
Q measurement
public-key cryptosystem
public-key cryptography
public-key algorithm
public key cryptography
pubcrawl
Montgomery modular multiplication
automation
Modular Multiplication
modular exponentiation on large number
modular exponentiation
mechatronics
logic design
frequency 170.0 MHz
FPGA
field programmable gate arrays
fast modular exponentiation algorithm
exponentiation
Erbium
Conferences

biblio

Optimizing Quantum Circuits for Modular Exponentiation

Submitted by aekwall on Mon, 01/20/2020 - 10:48am

pubcrawl
verilog implementation
tools
scalable synthesis methods
Scalability
reversible modular exponentiation function
Resiliency
Qubit
Quantum error correction
Quantum Error Correcting Codes (QECC)
quantum computing
quantum computers
quantum circuits
quantum architectures
Quantum Algorithm(QA)
computer architecture
modular exponentiation functions
modular exponentiation
Logic gates
logic designs
logic design
logic circuits
linear nearest neighbor property
Linear Nearest Neighbor (LNN)
Hardware design languages
hardware description languages
exponentiation functions
exponentiation
error correction

biblio

Routing Aware and Runtime Detection for Infected Network-on-Chip Routers

Submitted by grigby1 on Mon, 11/04/2019 - 11:39am

NoC
Trojan horses
system-on-chip
System recovery
security attacks
security
secure routing algorithm
secret key leaking
runtime detection
Runtime
Routing
Router Systems Security
Resiliency
resilience
pubcrawl
outsourcing
network on chip security
network-on-chip architecture
network-on-chip
network routing
Multiprocessors System-on-Chip
multiprocessing systems
MPSoC
Metrics
Malicious-tolerant Routing Algorithm
malicious Hardware Trojans
logic design
invasive software
integrated circuits
hardware trojan
Hardware

biblio

Variation-Aware Hardware Trojan Detection through Power Side-Channel

Submitted by grigby1 on Fri, 03/15/2019 - 10:59am

integrated logic circuits
variation-aware hardware Trojan detection
Trojan-to-circuit power consumption
Trojan horses
trojan horse detection
side-channel analysis
Sensitivity
pubcrawl
process variation
power side-channel
Power demand
outsourcing
logic design
invasive software
Clock-tree Partition
integrated circuits
integrated circuit testing
HT detection sensitivity
HT activation chances
hardware trojan
Hardware
fine-grain circuit partitioning
Equal-power Partition
Detection sensitivity
Detectability
Cryptography
Clocks

biblio

Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

Submitted by grigby1 on Mon, 06/11/2018 - 2:48pm

processed data
Metrics
Microelectronics Security
PAA
power analysis attacks
power consumption
Power dissipation
private key cryptography
probability
Probability distribution
low-power electronics
pubcrawl
resilience
Resiliency
secret cryptographic keys
secured dual-rail-precharge mux
side channel attack
Signal to noise ratio
Switches
DPMUX symmetric-logic
average power dissipation
clock cycle
combinatorial logic
composability
cryptographic algorithms
Cryptography
delays
deterministic power
Digital circuits
activity factor
dynamic switching energy
Hardware implementations
Information Leakage
linear relationship
logic circuits
logic design
Logic gates
low voltage applications

biblio

Combinational Hardware Trojan Detection Using Logic Implications

Submitted by grigby1 on Wed, 04/11/2018 - 2:00pm

logical implications
valid logic implications
Trojan horses
trojan horse detection
security
Resiliency
resilience
pubcrawl
proof-of-concept demonstration
potential benefit
Payloads
combinational circuits
logic simulation
Logic gates
logic design
invasive software
Integrated circuit modeling
Hardware
cyber physical systems
composability
combinational hardware trojan detection

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Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

logic design

Resilient Reorder Buffer Design for Network-on-Chip

Special Session: Countering IP Security Threats in Supply Chain

Increasing the SAT Attack Resiliency of In-Cone Logic Locking

Hardware Trojan Insertion and Detection in Asynchronous Circuits

Research in Fast Modular Exponentiation Algorithm Based on FPGA

Optimizing Quantum Circuits for Modular Exponentiation

Routing Aware and Runtime Detection for Infected Network-on-Chip Routers

Variation-Aware Hardware Trojan Detection through Power Side-Channel

Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

Combinational Hardware Trojan Detection Using Logic Implications